Renesas M16C/6V, Руководство пользователя

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7.4 Timing Requirements
Table 7.4 and Figure 7.4 show timing requirements when using the memory expansion mode and
microprocessor mode.
Table 7.4 Timing requirements (Vcc = 5 V)
Note 1. tsu(HOLD-BCLK) = 10
9 x
3 + 20
f(BCLK) x 2
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
Min.
40
30
40
0
0
0
-
Max.
-
-
-
-
-
-
40
Max.
-
-
-
-
-
-
40
Symbol Parameter
M306V0EEFP
[ns]
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
th(BCLK-HLDA)
M306V0T-RPD-E
[ns]
Min.
80
50
(Note 1)
0
0
0
-