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R-IN32M4-CL3 User's Manual: Board design edition

7. 2.5-V built-in Regulator Peripheral Circuit Configuration

R18UZ0074EJ0100

Page 23 of 61

Dec 24, 2019

7.5

Example of PCB Layout Image (23 mm Square BGA Package)

This section describes the peripheral circuit configuration of the 2.5-V built-in regulator installed in the R-IN32M4-CL3

in a 23 mm square BGA package.

7.5.1

L1 and L2 (23 mm Square BGA Package)

Followings are layout conditions and an example of PCB layout image (at the lower left of the L1 and L2).



Separate AGND of the built-in regulator from Digital GND as far as possible.



Do not pass through AGND under the MDI signal and the inductor component (L).

AGND

P0_

D0N

P0_

D0P

P0_

D1N

P0_

D1P

P0_

D2N

P0_

D2P

P0_

D3N

P0_

D3P

P0_

D0N

P0_

D0P

P0_

D1N

P0_

D1P

P0_

D2N

P0_

D2P

P0_

D3N

P0_

D3P

AVDD
REG_

AGND

REG_

OUT

REG_

VDD

REG_

AVDD
REG_

AGND

REG

_FB

REG_

OUT

REG_

VDD

REG_

VDD

PCB L1

Connect to AGND of C

and C

OUT

GND

GND/

OPEN

GND/

OPEN

GND/

OPEN

GND/

OPEN

GND

Do not pass AGND under the
MDI signal and the inductor
component (L).

VDD

11A

VDD

11A

VDD

11A

VDD

11A

Connect to GND at a single-point ground in front of this.
(In this case, do not use a ferrite bead.)

Removing the pattern

AGND

PCB L2 (GND)

Figure 7.3 Example of PCB Layout Image (L1 and L2) (23 mm Square BGA Package)

7.5.2

L3 and L4 (23 mm Square BGA Package)

Followings are layout conditions and an example of PCB layout image (at the lower left of the L3 and L4).



Place C

BYPASS

as close to the power supply pins (VDDREG_33 and AVDDREG_33).

Also, place L, C

, and C

OUT

as close to the relevant pins as possible. In particular, placement of C

is a high

priority.



Minimize the parasitic inductance of AVDDREG_33 pattern as small as possible.

The AVDDREG_33, AGND, and REG_OUT signals should be careful to avoid affecting other signals.

AGN

AGND

GND/

OPEN

P0_

D0N

P0_

D0P

P0_

D1N

P0_

D1P

P0_

D2N

P0_

D2P

P0_

D3N

P0_

D3P

P0_

D0N

P0_

D0P

P0_

D1N

P0_

D1P

P0_

D2N

P0_

D2P

P0_

D3N

P0_

D3P

AVDD

REG_3

AGND

REG_

OUT

REG_

VDD

REG_3

AVDD
REG_

AGND

REG_

OUT

REG_

VDD

REG_

VDD

11A

VDD

11A

GND/

OPEN

GND/

OPEN

GND/

OPEN

VDD

11A

VDD

11A

VDD

REG_
FB

Minimize parasitic inductance
to AVDDREG_33.

BYPASS

REG_OUT

Place SBD, L, and C

OUT

compactly in front

of this to connect to the PCB.
Don't make an unnecessarily wide pattern
to avoid functioning as an antenna.

This pattern is a 2.5-V feedback voltage after smoothing with the
inductor (L) and capacitor (C

OUT

Keep away from the regulator related signals and the inductor (L).

Bypass capacitor for
AVDDREG_33
Connect to AGND

Bypass capacitor for
VDDREG_33
Connect to GND

L3 at this position, where L2 is AGND,
is preferably AGND than other power
sources.

Removing the pattern

AVDDREG_33

BYPASS

PCB L3 (VDD)

PCB L4

OUT

SBD

Place C

BYPASS

as close to the power supply pin (VDDREG_33 and AVDDREG_33).

Also, place C

as close to the relevant pin as possible. (Placement of C

is high priority

than that of SBD, inductor, and C

OUT

Do not place C

and C

OUT

side by side to prevent noise propagation.

SBD: Schottky Barrier Diode

Figure 7.4 Example of PCB Layout Image (L3 and L4) (23 mm Square BGA Package)

Содержание IAR KickStart Kit R-IN32M4-CL3

Страница 1: ...esents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics C...

Страница 2: ...g out of the use of Renesas Electronics products outside of such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products semico...

Страница 3: ...duced in the vicinity of the LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible 5 Clock si...

Страница 4: ...e related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Please be understanding of this beforehand In addition because we...

Страница 5: ...xxnx pin name or signal name contains small letter n Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary xx...

Страница 6: ...le of Oscillation Circuits 9 4 PLL Power Supply Pins 10 4 1 Recommended Configuration of Filter 10 4 2 Notes on Placement of Peripheral Components 11 5 GPIO Port Pins 12 6 Gigabit Ethernet PHY Pins 13...

Страница 7: ...ic Resistances and Parasitic Inductances in PCB 25 8 Thermal Design 26 8 1 Deciding on whether Particular Measures for Heat Dissipation are Required 26 8 1 1 Estimating Tj 26 8 1 2 Estimating Power Co...

Страница 8: ...and Two Slaves 49 15 JTAG Trace Pins 50 16 Implementation Conditions 54 17 Package Information 55 18 Mount Pad Information 57 19 BSCAN Information 58 19 1 BSCAN Operating Conditions 58 19 2 Maximum O...

Страница 9: ...2 Peripheral Connection Configuration without 2 5 V built in Regulator 21 Figure 7 3 Example of PCB Layout Image L1 and L2 23 mm Square BGA Package 23 Figure 7 4 Example of PCB Layout Image L3 and L4...

Страница 10: ...ween One Master and Two Slaves 49 Figure 15 1 Connection Example of JTAG Interface 20 Pin Half Pitch without Trace 50 Figure 15 2 Connection Example of JTAG Interface 20 Pin Half Pitch with Trace 51 F...

Страница 11: ...le 7 1 Example of Recommended Component of Inductor 22 Table 7 2 Capacitance Definition CIN COUT 22 Table 7 3 Example of Recommended Components of Ceramic Capacitors 22 Table 7 4 Example of Recommende...

Страница 12: ...de by Renesas Electronics The target device is the R IN32M4 CL3 It is recommended to study this manual carefully and to follow the recommendations during the circuit and board design 1 1 Definition of...

Страница 13: ...irst and then supplying external power voltage VDD33 On the other hand when turning off the power disconnect VDD33 then VDD11 If VDD33 is supplied first note that the I O modes of the I O buffers are...

Страница 14: ...ms 2 Turning Off Power Voltages Turn off power voltages so that the following two conditions are both satisfied 1 The period from when VDD33 VDD25 or VDD11 reaches 90 VDD to when all of them reach 10...

Страница 15: ...within 49 ms 2 Turning Off Power Voltages Turn off power voltages so that the following two conditions are both satisfied 1 The period from when VDD33 or VDD11 reaches 90 VDD to when both of them reac...

Страница 16: ...M4 internal power supply 1 15 V Supply power from the power unit such as a regulator or DC DC converter GND Ground potential for power supply GND Connect GND of the system board VDD25A GbE PHY analog...

Страница 17: ...evel of the reset signal over the oscillation stabilization time of the external oscillator 25 MHz In addition de assert the RESETZ and HOTRESETZ signals after de asserting the PONRZ signal Pin Name F...

Страница 18: ...ive XT1 to the low level XT2 Input Connects an external oscillator In external clock input mode OSCTH 1 the clock signal from an external oscillator is input via XT2 OSCTHNote Input Selects the clock...

Страница 19: ...s far as possible from high frequency input pins such as clock pins Place the resonators and components for external constants immediately close to the input and output pins of oscillation circuit and...

Страница 20: ...r it may not be required depending on the resonator to be used In external clock input mode drive XT1 to the low level R IN32M4 CL3 R IN32M4 CL3 VDD33 3 3 V Figure 3 2 Configuration Example of the Osc...

Страница 21: ...e use of ferrite beads is recommended 4 1 Recommended Configuration of Filter Figure 4 1 shows the recommended configuration of the filter for the PLL power supply pins C1 PLL PLL_GND PLL_VDD R IN32M4...

Страница 22: ...iring patterns for the electrolytic capacitor C2 and ferrite beads running parallel to other signal lines should be avoided PLL_ GND PLL_ VDD C1 Pay particular attention to the effects of noise from s...

Страница 23: ...ort Pins R18UZ0074EJ0100 Page 12 of 61 Dec 24 2019 5 GPIO Port Pins GPIO is a general purpose I O port As for the internal configuration see the section in the following document Section 27 Port Funct...

Страница 24: ...power Place these capacitors as close to the respective power source pins as is possible 1 15 V power plane 2 5 V power plane Decoupling capacitors bypass capacitors Placing one within 0 5 inches of...

Страница 25: ...Part Number Capacitance TDK C32165R1C476M1160AB 47 F TDK C2012X5R1C106K085AC 10 F 2 Ferrite beads We recommend using components that satisfy the following conditions Impedance At least 80 at 100 MHz U...

Страница 26: ...sformer An example of the circuit configuration for the Gigabit Ethernet PHY pulse transformers and RJ 45 connector and recommended pulse transformer products are shown below 6 2 1 Example of Circuit...

Страница 27: ...CL3 PHY side and is mounted on the connector Winding ratio 1 1 2 or less or 3 recommended Return loss see Figure 6 4 18dB or less from 1 0 MHz to 40 MHz 12 20log f 80 dB or less from 40 MHz to 100 MHz...

Страница 28: ...m that for other high frequency signals but place the components close to the pins Join the wires at a single point and connect this to GND Place GND wiring as a guard Figure 6 5 Example of Circuit Co...

Страница 29: ...ed in the same layer Placement of components via holes and the like should also be symmetrical Branches in signal lines act as stubs and should thus be avoided Place traces for differential signals wi...

Страница 30: ...Manual Board design edition 6 Gigabit Ethernet PHY Pins R18UZ0074EJ0100 Page 19 of 61 Dec 24 2019 Figure 6 7 Example of Wiring for Differential Signals 2 g g w w s Figure 6 8 Example of Wiring for Dif...

Страница 31: ...ple of Wiring for Differential Signals 4 6 5 Unused GbE PHY Comply with the following requirements even when GbE PHY is not in use Always power supply to the VDD25A and VDD11A pins The method of handl...

Страница 32: ...nt the undershoot voltage increases and 2 5 V potential after smoothing rises To avoid it the undershooting has to suppress by SBD Place these SBD L and COUT close to the REG_OUT pin Place this capaci...

Страница 33: ...m from 700 kHz to 1 3 MHz Table 7 2 Capacitance Definition CIN COUT C Capacitance lower limit upper limit CIN 47 F 10 F no definition COUT 47 F 14 F 200 F Select the components in considering the DC...

Страница 34: ...CBYPASS as close to the power supply pins VDDREG_33 and AVDDREG_33 Also place L CIN and COUT as close to the relevant pins as possible In particular placement of CIN is a high priority Minimize the pa...

Страница 35: ...onnect to GND at a single point ground in front of this In this case do not use a ferrite bead Minimize parasitic inductance to AVDDREG_33 Bypass capacitor for AVDDREG_33 Connect to AGND Bypass capaci...

Страница 36: ...ic resistances and the parasitic inductances satisfy the followings Table 7 5 Requirements for Parasitic Resistances and Parasitic Inductances in PCB Ball 23 mm Square BGA Package Ball 17 mm Square BG...

Страница 37: ...l Resistances under the JEDEC Conditions for ja and jt Power Power dissipation W 1 15 V sub systems 2 5 V sub systems 3 3 V sub systems If Tj 125 C is satisfied the semiconductor device does not requi...

Страница 38: ...er Note1 IV Consider other factors of placement that will affect heat flows and take the appropriate action Note2 2 Heat dissipation from the periphery including the casing If the measures listed in 1...

Страница 39: ...t dissipation Therefore place the GND pattern in such a way that the paths are divided as little as is possible We recommend L2 for the GND layer 3 Increase the Number of Board Layers and Bring the GN...

Страница 40: ...io in all layers of the board layers increases the breadth of the paths for heat transfer 6 Cu Thickness Designing all Cu layers of the board to be thick increases the volume of paths for heat dissipa...

Страница 41: ...Casing Including a fan improves thermal conductivity through convection which decreases the ambient temperature 4 Obtaining a Chimney Effect Since heat tends to be released in the z direction placing...

Страница 42: ...e other hand if an unused pin is open circuit on the board the corresponding pin can have either the output attribute or the input attribute as a fixed setting accompanied by enabling of the pull up o...

Страница 43: ...ernal memory interface Asynchronous SRAM MEMC High External memory interface Synchronous burst access MEMC High Low Low External MCU interface Asynchronous SRAM supporting MCU connection mode High Ext...

Страница 44: ...FSYNC pin is high it functions as a synchronous SRAM interface and when HIFSYNC is set to low level it functions as an asynchronous SRAM interface see Table 9 1 Mode Selection of External MCU Memory C...

Страница 45: ...Connection Mode R IN32M4 CL3 External MCU A1 A20 D0 D15 CSZ HPGCSZNote3 HA1 HA20Note5 HD0 HD15 PGCSZ RDZ HCSZ HRDZ WAITZ HWAITZ WRSTBZ HWRSTBZ Interrupt port pin HERROUTZNote2 HBUSCLK HWRZ0 HBENZ0Note...

Страница 46: ...onnection Mode R IN32M4 CL3 External MCU A1 A20 D0 D15 CSZ HPGCSZNote3 HA1 HA20Note5 HD0 HD15 PGCSZ RDZ HCSZ HRDZ WAITZ HWAITZ WRSTBZ HWRSTBZ Interrupt port pin HERROUTZNote2 HWRZ0 HBENZ0Note1 WRZ0 BE...

Страница 47: ...MCU D0 D31 CSZ HBCYSTZ HD0 HD31 BCYSTZ ADV RDZ HCSZ HRDZ WAITZ HWAITZ WRSTBZ HWRSTBZ Interrupt port pin HERROUTZNote2 HBUSCLK HWRZ0 HBENZ0 BENZ0 BENZ1 BENZ2 BENZ3 HWRZ1 HBENZ1 HWRZ2 HBENZ2 HWRZ3 HBENZ...

Страница 48: ...this mode drive the HWRZSEL pin low 2 Connecting the HERROUTZ signal is not indispensable Connect it to an interrupt or general purpose port input of the MCU to be connected if required 3 Connected t...

Страница 49: ...External MCU D0 D15 PGCSZ HBCYSTZ HD0 HD15 BCYSTZ ADV RDZ HPGCSZ HRDZ WAITZ HWAITZ WRSTBZ HWRSTBZ Interrupt port pin HERROUTZNote2 HWRZ0 HBENZ0 BENZ0 BENZ1 HWRZ1 HBENZ1 HBUSCLK BUSCLK A1 A20Note4 HA1...

Страница 50: ...on of External MCU Memory Connection 9 2 1 Asynchronous SRAM MEMC The asynchronous SRAM MEMC is externally connectable to paged ROM ROM SRAM or peripheral devices with an interface similar to the SRAM...

Страница 51: ...19 D16 D31 CSZn SRAM 256 Kwords 16 bits A0 A17 I O1 I O16 CS UB WE OE LB WRZ3 BENZ3 WRZ2 BENZ2 WRZ1 BENZ1 WRSTBZ D0 D15 WRZ0 BENZ0 SRAM 256 Kwords 16 bits A0 A17 I O1 I O16 CS UB WE OE LB Figure 9 9 C...

Страница 52: ...CL3 RDZ A2 A21 D16 D31 CSZ0 D0 D15 Paged ROM 1 Mword 16 bits A0 A19 O0 O15 CE OE WRSTBZ WE Paged ROM 1 Mword 16 bits A0 A19 O0 O15 CE OE WE Figure 9 11 Connection Example with 32 Bit Paged ROM Asynch...

Страница 53: ...SRAM interface via a 16 or 32 bit bus In addition setting the ADMUXMODE pin to the high level enables multiplexing of the address and data signals The external MCU interfaces for the synchronous metho...

Страница 54: ...1 WRSTBZ D0 D15 WRZ0 BENZ0 BUSCLK BUSCLK SRAM 256 Kwords 16 bits A0 A17Note I O1 I O16 CS UB WE OE LB BUSCLK Figure 9 13 Connection Example with 32 Bit SRAM Synchronous Burst Access MEMC R IN32M4 CL3...

Страница 55: ...K Paged ROM 1 Mword 16 bits A0 A19Note O0 O15 CE OE WE BUSCLK Figure 9 15 Connection Example with 32 Bit Paged ROM Synchronous Burst Access MEMC R IN32M4 CL3 Paged ROM 1 Mword 16 bits A0 A19Note O0 O1...

Страница 56: ...erial Flash ROM Connection Pins This LSI chip has a memory controller to connect the serial flash ROM that supports the SPI compatible interface R IN32M4 CL3 Serial flash memory C CLK D IO0 SMSCK P14...

Страница 57: ...019 11 Asynchronous Serial Interface J Connection Pins The following figure shows a connection example between the R IN32M4 CL3 and the asynchronous serial interface J UARTJ device R IN32M4 CL3 RXD0 P...

Страница 58: ...device Since the serial clock line and serial data line are N channel open drain outputs an external pull up resistor is required R IN32M4 CL3 Clock output VDD33 3 3 V SCLn Clock input Data output Dat...

Страница 59: ...he following figure shows a connection example between the R IN32M4 CL3 and the CAN transceiver The CAN transceiver is used to connect the CAN bus R IN32M4 CL3 CAN transceiver Rxd Txd CRXD0 P53 CRXD1...

Страница 60: ...CL3 Slave Master CSISCKn in CSISIn CSISOn SCK out MOSI MISO Figure 14 1 Direct Master Slave Connection Remark n 0 1 14 2 One Master and Two Slaves The following figure illustrates the connections betw...

Страница 61: ...e internal PLL is not reset in the case of only HOTRESETZ Please use it to meet your needs In addition nRESET should not be connect to PONRZ They are examples when connected to the 20 pin half pitch c...

Страница 62: ...to 10 k TRACECLK TRACEDATA0 TRACEDATA1 TRACEDATA2 TRACECLK TRACEDATA0 TRACEDATA1 TRACEDATA2 TRACEDATA3 TRACEDATA3 JTAGSEL About 22 to 33 The wiring runs should preferably be no longer than 50 mm If th...

Страница 63: ...SWCLK ICE connecter 20 pin half pitch TCK SWCLK TMS SWDIO TDI TDO TMS SWDIO TDI TDO TRSTZ nRESET RESETZ HOTRESETZ Reset circuit VDD33 3 3 V About 4 7 k to 10 k JTAGSEL Wired OR connection with open dr...

Страница 64: ...3 of 61 Dec 24 2019 R IN32M4 CL3 TCK ICE connecter 20 pin full pitch TCK TMS TDI TDO TMS TDI TDO TRSTZ nSRST RESETZ HOTRESETZ Reset circuit About 4 7 k to 10 k JTAGSEL nTRST Wired OR connection with o...

Страница 65: ...emperature less than 70 humidity Figure 16 1 Implementation Flow Maximum temperature package surface temperature 250 C or below Time of maximum temperature 30 s or less Time over which the temperature...

Страница 66: ...rd design edition 17 Package Information R18UZ0074EJ0100 Page 55 of 61 Dec 24 2019 17 Package Information The following figures show the package information of R IN32M4 CL3 Figure 17 1 Package Informa...

Страница 67: ...R IN32M4 CL3 User s Manual Board design edition 17 Package Information R18UZ0074EJ0100 Page 56 of 61 Dec 24 2019 Figure 17 2 Package Information 17 mm Square BGA Package...

Страница 68: ...Pad Information The following figures show the mount pad information of the R IN32M4 CL3 1 00 mm 0 43 to 0 53 mm 0 50 to 0 70 mm 1 00 mm 0 43 to 0 53 mm Figure 18 1 Mount Pad Sizes 23 mm Square BGA P...

Страница 69: ...0 Fixed to the low level TMODE1 Fixed to the low level TMODE2 Fixed to the low level 19 2 Maximum Operating Frequency of TCK The maximum operating frequency of TCK is 10 MHz 19 3 IDCODE IDCODE is as f...

Страница 70: ...User s Manual Board design edition 20 IBIS Information R18UZ0074EJ0100 Page 59 of 61 Dec 24 2019 20 IBIS Information For IBIS information please contact a Renesas Sales Representative or Distributor...

Страница 71: ...R18UZ0074EJ0100 Page 60 of 61 Dec 24 2019 21 Marking Information The following figures show the marking information of R IN32M4 CL3 Figure 21 1 R IN32M4 CL3 Marking Information 23 mm Square BGA Packag...

Страница 72: ...noise in circuits that include an R IN32M4 CL3 22 1 Stopping Clock Output If the BUSCLK pin is not in use output on the pin from the R IN32M4 CL3 can be stopped See Section 4 2 2 Clock Control Registe...

Страница 73: ...N32M4 CL3 User s Manual Board design edition REVISION HISTORY C 1 REVISION HISTORY R IN32M4 CL3 User s Manual Board design edition Rev Date Description Page Summary 1 00 Dec 24 2019 First edition issu...

Страница 74: ...R IN32M4 CL3 User s Manual Board design edition REVISION HISTORY C 2 MEMO...

Страница 75: ...R IN32M4 CL3 User s Manual Board design edition Publication Date Rev 1 00 Dec 24 2019 Published by Renesas Electronics Corporation...

Страница 76: ...R IN32M4 CL3 User s Manual Board design edition R18UZ0074EJ0100...

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