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HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 22 of 29

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Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address
H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.

D15 of address H’F8 = 0

D15 of address H’F8 = 1

Divided mode

2 divided, 1/4 phase select

3 divided, 1/6 phase select

D0 to D7 of address H’F5

Valid

Invalid

D0 to D14 of address H’F8

Invalid

Valid

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Phase settings of high speed pulse (address H’F5 to H’F8)
(1) Select the 1/4 phase from figure 13 at 2 divided mode (D15 = 0 of address H’F8).

Select the 1/6 phase from figure 14 at 3 divided mode (D15 = 1 of address H’F8).
·····P_SP1, P_SP2, P_ADCLK, P_RG

(2) Then select the necessary delay time from figure 15.

·····DL_SP1, DL_SP2, DL_RG, DL_ADCLK
RG can be set both of rising / falling edge optionally.

Data = 0

Data = 1

Data = 3

Data = 2

P_SP1
P_SP2

Data = 0

Data = 1

Data = 3

Data = 2

P_ADCLK
P_RG

Figure 13 2 Divided Mode, 1/4 Phase Select

(Valid at D15 = 0 of address H’F8)

Data = 5

Data = 2

Data = 3

Data = 4

Data = 1

Data = 0

P_SP1
P_SP2

Data = 0

Data = 3

Data = 4

Data = 5

Data = 2

Data = 1

P_ADCLK
P_RG

Figure 14 3 Divided Mode, 1/6 Phase Select

(Valid at D15 = 1 of address H’F8)

Default Value of Each Phases

P_SP1

P_SP2

P_ADCLK P_RG

divided

mode

1 2 1 0

divided

mode

0 3 1 5

Note: 50% of duty pulse makes tr, tf of RG by DLL.

Address

STD1[7:0] (L)

STD2[15:8] (H)

D12 D11 D10 D9

DL_SP2

DL_SP1

DL_RG_f

DL_RG_r

DL_ADCLK

CDS_test

Address

STD1[7:0] (L)

STD2[15:8] (H)

D12 D11 D10 D9

Dummy

clamp th

Dummy

clamp current

Содержание HD49335HNP

Страница 1: ...g frequency Power dissipation 220 mW Typ maximum frequency 36 MHz HD49335HNP Power dissipation 150 mW Typ maximum frequency 25 MHz HD49335NP ADC direct input mode QFN 64 pin package Features Suppresse...

Страница 2: ...O D 2 mA 10 pF 2 DVSS1 2 CDS Digital ground ADC output buffer ground 0 V D 3 to 12 D0 to D9 Digital output D0 LSB D9 MSB O D 2 mA 10 pF 13 DVDD2 ADC output buffer power supply 3 V D 14 DVSS3 General...

Страница 3: ...und 0 V A 44 ADC_in AD converter input pin I A 45 BIAS Bias standard resistance A 46 VRB ADC bottom standard voltage 0 1 F for GND A 47 VRT ADC top standard voltage 0 1 F for GND A 48 VRM ADC middle s...

Страница 4: ...t ID RG MON XV1 to XV4 CH1 to CH4 XSUB DIN DVDD Digital output Digital input CLK_in HD_in VD_in ADCLK OBP SPBLK SPSIG CS SCK SDATA PBLK OEB Reset Test1 Test2 SUB_SW STROB 1 Digital input DVDD Note Onl...

Страница 5: ...STROB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reset DVSS1 to 4 BLKFB CS SDATA SCK DLL_C MON ID BIAS Timing generator VD_in HD_in CLK_in XSUB CH4 CH3 CH2 CH1 XV4 XV3 PBLK CPDM OBP ADCLK SP2 SP1 XV2 XV1 1 4clk_o...

Страница 6: ...10bit ADC D0 to D9 BLKC C4 OBP ADC_in Offset calibration logic DC offset feedback logic Gain setting register Clamp data register Current DAC Figure 1 CDS PGA Functional Block Diagram 1 CDS Correlate...

Страница 7: ...or Example When fclk 20 MHz and C3 1 0 F Gain H 0 0039 When the PGAMP gain setting is changed the high speed lead in operation state is entered and the feedback loop gain is increased by a multiple of...

Страница 8: ...0 are inverted in table 5 D9 to D0 are inverted in table 5 Output code is set up to Clamp Level Low power wait state Normal operation Pre blanking Normal operation Pre blanking Test mode Operating Mod...

Страница 9: ...87 nsec 27 MHz 6 60 nsec 24 MHz 8 80 nsec 18 MHz 10 6 nsec 15 MHz 17 6 nsec 9 MHz 26 4 nsec 6 MHz L 3 H 3 H 0 H 0 L 1 L 1 L 2 L 2 L 3 H 3 L 0 L 0 H 1 H 1 L 2 L 2 L 3 H 3 H 0 H 0 H 1 H 1 L 2 L 2 L 3 H...

Страница 10: ...N 1 ADC_in ADCLK D0 to D9 N N 1 N N 1 N 9 N 8 N 1 N N 10 When CDS_in input mode is used When ADC_in input mode is used Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used The ADC ou...

Страница 11: ...falling to SP2 falling time tCDS5 Typ 0 85 1 2fCLK Typ 1 15 ns 6 SP1 falling to ADCLK rising inhibit time tCDS6 5 ns 7 8 ADCLK tWH min tWL min tCDS7 8 11 ns 9 ADCLK rising to digital output holding ti...

Страница 12: ...ADCIN Input Mode is Used Figure 6 shows the detailed timing chart when ADCIN input mode is used and table 9 shows each timing specification ADC_in 1 ADCLK D0 to D9 2 Vth VDD 2 3 5 4 Figure 6 Detailed...

Страница 13: ...7 Dummy CP 0 0 0 OFF 0 0 1 32 0 1 0 64 0 1 1 96 1 1 1 224 The amount of offset are changes automatically depends on PGA gain in the LSI D8 D8 of address H F7 DMCG The amount of feed back current can b...

Страница 14: ...ide specified Ta 25 C AVDD 3 0 V DVDD 3 0 V and RBIAS 33 k Items Common to CDSIN and ADCIN Input Modes Item Symbol Min Typ Max Unit Test Conditions Remarks Power supply voltage range VDD 2 70 3 00 3 3...

Страница 15: ...tions 12 tCDS12 1 fCLK ns Timing specifications 13 tCDS13 1 2fCLK ns Refer to table 8 CLP 00 14 LSB CLP 09 32 LSB Clamp level CLP 31 76 LSB AGC 0 4 4 2 4 0 4 dB AGC 63 4 1 6 1 8 1 dB AGC 127 12 5 14 5...

Страница 16: ...g specifications 14 tADC1 6 ns Timing specifications 15 tADC2 Typ 0 85 1 2fADCLK Typ 1 15 ns Timing specifications 16 tADC3 Typ 0 85 1 2fADCLK Typ 1 15 ns Timing specifications 17 tAHLD4 14 5 ns CL 10...

Страница 17: ...tho 50 ns Notes 1 3 byte continuous communications 2 Input SCK with 24 clock when CS is Low 3 It becomes invalid when data communications are stopped on the way 4 Data becomes a default with hardware...

Страница 18: ...d be decided that how much dB add on 1 Level dia explain CDS PGA 0 dB when set N 18 which correspond to 2 36 dB ADC 2 Level dia on the circuit CDS PGA 3 64 dB 0 132 dB N CDS 0 dB ADC 2 V 1023 1 0 V 1...

Страница 19: ...0 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 Clamp level Reset AD_sel CDS_buff Low_pwr HGstop Hsel Clamp D0 to D4 of address H F2 Determine the OB part level with digital code of ADC output Clamp l...

Страница 20: ...ch D7 of address H F4 Data 0 Gain data is determined when CS rising Data 1 Gain data is determined when VD falling Differential Code and Gray Code D8 to D12 of address H F4 Gray code D8 to D9 of addre...

Страница 21: ...trol signal D12 D11 D10 Standard data selector 10 bit output 2clk_DL Gray Binary conversion Figure 10 Differential Code Gray Code Circuit 1 ADCLK OBP Digital output Beginning edge of OBP and standard...

Страница 22: ...select the necessary delay time from figure 15 DL_SP1 DL_SP2 DL_RG DL_ADCLK RG can be set both of rising falling edge optionally H1 Data 0 Data 1 Data 3 Data 2 P_SP1 P_SP2 H1 Data 0 Data 1 Data 3 Data...

Страница 23: ...ps with 1 step 1 ns or 2 ns divide Select the 2 ns divide when sensor CLK is less than 15 MHz DL_RG DL_SP1 DL_ADCLK DL_SP2 DL_ADCLK DLL_C Control voltage P_ADCLK AND PC DLL 64 steps ADCLK 0 In phase w...

Страница 24: ...6clk or more 1 2ms or more Charge of external C 40 000ADCLK or more offset calibration 2 3 4 CDS_Reset Low 5 Note At 2 divided mode ADCLK 1 2CLK_in At 3 divided mode ADCLK 1 3CLK_in SP1 SP2 ADCLK OBP...

Страница 25: ...tem H1 H2 RG XV1 to 4 CH1 to 4 XSUB SUB_SW min 14 7 typ 20 10 twh max min 14 typ 20 37 twl max min typ 8 0 4 0 20 20 20 tr max 14 min typ 8 0 4 0 20 20 20 tf max 14 165 pF 15 pF 15 pF 15 pF 15 pF Load...

Страница 26: ...nalog system and digital system set grounds connect to the analog system 7 When VDD is specified in the data sheet this indicates AVDD and DVDD 8 No Connection NC pins are not connected inside the IC...

Страница 27: ...10 9 8 7 6 5 4 3 2 1 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 32 50 57 58 59 60 61 62 63 64 56 55 54 53 52 51 49 HD49335 1 1 0 1 47 6 47 6 1000p 100p XV4 CH1 CH2 CH3 CH4 XSUB SUB_SW ADCK_in SUB_PD...

Страница 28: ...0 0 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 D01 Low Low Low High Low Low Low High Low X High High Low Low Low High High Low High Low High High High High High Resiste...

Страница 29: ...Package Code JEDEC JEITA Mass reference value TNP 64AV 0 14 g Unit mm 1 9 0 20 0 05 0 05 M 0 05 S S A B C A B C 8 80 0 65 C0 50 Index 0 50 Part A 0 2 S Enlargement of Part A C 0 1 0 0 1 6 0 2 0 3 8 2...

Страница 30: ...a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting f...

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