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(2) Separate Bus, With Wait, Accessing External Memory Area
Table 5.3 and Figure 5.2 show the bus timing in the memory expansion mode and the microprocessor
mode (with wait, accessing external memory area).
Table 5.3 Memory expansion mode and microprocessor mode (with wait, external memory area)
*1 Calculated by the following formula according to the frequency of BCLK.
Td (DB-WR)=
10
9
f(BCLK)
-40 [ns]
Td (BCLK-AD)
Th (BCLK-AD)
Th (RD-AD)
Th (WR-AD)
Td (BCLK-CS)
Th (BCLK-CS)
Td (BCLK-ALE)
Th (BCLK-ALE)
Td (BCLK-RD)
Th (BCLK-RD)
Td (BCLK-WR)
Th (BCLK-WR)
Td (BCLK-DB)
Th (BCLK-DB)
Td (DB-WR)
Th (WR-DB)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
Min.
4
0
0
4
-4
0
0
4
(*1)
0
Max.
25
25
25
25
25
40
Min.
Max.
Actual MCU
[ns]
This product
[ns]
Symbol
Item
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See left
See left
See left
See left
See left
See left
See left
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See left
See left
See left
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Содержание Emulation Pod M30620T2-RPD-E
Страница 3: ...M30620T2 RPD E User s Manual User s Manual Rev 1 00 2003 07 Emulation Pod for M16C 62 62A Group MCUs...
Страница 8: ...6 78 MEMO...
Страница 38: ...36 78 MEMO...
Страница 44: ...42 78 Figure 4 4 Self check procedure...
Страница 65: ...63 78 Figure 5 12 Connection diagram 2...
Страница 68: ...66 78 MEMO...
Страница 78: ...76 78 MEMO...
Страница 80: ...1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan M30620T2 RPD E REJ10J0196 0100Z User s Manual...