Renesas 8A3 72QFN Series, Руководство пользователя

Страница: 11 / 25

R31UH0015EU0101 Rev.1.01 Page 11
Apr 26, 2022
8A3xxxx 72QFN Evaluation Kit Manual
10. In the case where the firmware version mismatches each other, a firmware upgrade is necessary to update the
device’s firmware. To update the device’s firmware, complete the Firmware Version Update steps in Appendix
A: How to Upgrade the Firmware .
2.3 Output Terminations and Rework to Take 1PPS Input
All outputs are terminated with a 100Ω resistor across the output pair. This is the recommended termination
regardless of the Voffset and Vswing settings. Since the outputs are DC-coupled, they will support a 1PPS output
without any need for rework.
Note : When connecting the outputs to measurement equipment, use a DC-block to ensure that the output
operates at its intended Voffset; otherwise, the equipment may load the output down and cause degraded
performance.
The following rework must be implemented in order to support a 1PPS input clock. All input clocks for the
evaluation board are AC-coupled and terminated as in
Figure 14. Input Clock’s AC-Coupling and Terminations
For a 1PPS input, a single-ended input with DC-coupling is recommended. As such, the populated AC-coupling
capacitor must be removed and the input must be configured as LVCMOS, not differential. In Figure 14 , to make
CLK0 supportive of 1PPS input, first configure CLK0 as LVCMOS in Timing Commander (see Figure 15 )
Figure 15. Configuring CLK0 as CMOS to Receive a 1PPS Input
Once in LVCMOS mode, CLK0_P and CLK0_N will be two separate LVCMOS inputs instead of a differential pair.
To make CLK0_P receive a 1PPS input, replace C881 with a 0Ω resistor, while at the same time, remove R765
and R770.