Publication No. REF-000-009-R00
Red Rapids
Page 5
Trim
DAC
Control
Interface
CS_LD
DIN
SCK
spi_csb(n)
spi_sdi
spi_clk
Device Configuration
(SPI Bus)
Figure 2-4 Trim DAC Control
2.4 ADC Configuration
The receiver ADC has a number of configuration options available to support different
modes of operation. The following sections describe the physical connection of the
device in terms of hardwired board connections, clock inputs and control/data
interfaces accessible to the user. Operational modes are described in the ADC device
data sheet listed in section 5.0. .
2.4.1 ADC Hardware Interface
Selected ADC component physical pin connections are shown in Figure 2-5. The
figure shows logical connection of the RX channel interface and individual discrete
control pins described in the device data sheet listed in section 5.0.
Receiver
ADC
TEST
SENSE
0
SYNC
PDWN
49.9
10.0k
10.0k
RBIAS
VREF
0.1 uF
1.0 uF
10.0k
Receiver
ADC
ADCA
ADCB
Analog RX CH 2
Analog RX CH 1
Figure 2-5 Selected RX ADC Physical Connections