Ameba-D User Manual
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Table 9-2 describes the hardware handshaking signals in the case where the peripheral is not the flow controller; that is, where either the
DMAC or the other peripheral is the flow controller. Signal polarity can be programmed using the CFGx.SRC_HS_POL and CFGx.DST_HS_POL
fields.
Table 9-2 Hardware handshaking interface
Signal
Direction
Description
dma_ack
Output
DMAC acknowledge signal to peripheral. The dma_ack signal is asserted after the data phase of the last AHB
transfer in the current transaction – single or burst – to the peripheral that has completed. For a single
transaction, dma_ack remains asserted until the peripheral de-asserts dma_single; dma_ack is de-asserted one
hclk cycle later. For a burst transaction, dma_ack remains asserted until the peripheral de-asserts dma_req;
dma_ack is de-asserted one hclk cycle later.
dma_finish
Output
DMAC asserts dma_finish to signal block completion. This has the same timing as dma_ack and forms a
handshaking loop with dma_req if the last transaction in the block was a burst transaction, or with dma_single
if the last transaction in the block was a single transaction. There is an exception to the above timing definition
when dma_finish interfaces with a source peripheral when the destination peripheral is the flow controller.
dma_last
Input
Since the peripheral is not the flow controller, dma_last is not sampled by the DMAC and this signal is ignored.
dma_req
Input
Burst transaction request from peripheral. The DMAC always interprets the dma_req signal as a burst
transaction request, regardless of the level of dma_single. This is a level-sensitive signal; once asserted by the
peripheral, dma_req must remain asserted until the DMAC asserts dma_ack. Upon receiving the dma_ack
signal from the DMAC to indicate the burst transaction is complete, the peripheral should de-assert the burst
request signal, dma_req. Once dma_req is de-asserted by the peripheral, the DMAC de-asserts dma_ack. If an
active level on dma_req is detected in the Single Transaction Region, then the block is completed using an
Early-Terminated Burst Transaction.
dma_single Input
Single transfer status. The dma_single signal is a status signal that is asserted by a destination peripheral when
it can accept at least one destination data item; otherwise it is cleared. For a source peripheral, the dma_single
signal is again a status signal and is asserted by a source peripheral when it can transmit at least one source
data item; otherwise it is cleared. Once asserted, dma_single must remain asserted until dma_ack is asserted,
at which time the peripheral should de-assert dma_single. This signal is sampled by the DMAC only in the
Single Transaction Region of the block transfer. Outside of this region, dma_single is ignored and all
transactions are burst transactions.
shows the timing diagram of a burst transaction where the peripheral clock, per_clk, equals hclk. In this example, the peripheral is
outside the Single Transaction Region, and therefore the DMAC does not sample dma_single[0].
The handshaking loop is as follows:
Fig 9-7 Burst transaction – pclk = hclk
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