RCA 70/46 Скачать руководство пользователя страница 50

Страница: 50 / 260

Содержание 70/46

Страница 1: ...5iPEL IRA u 70 46 Processor Reference Manual OOm3LlD Information Systems 70 46 601 March 1968 ...

Страница 2: ...The information contained herein is subject to change without notice Revisions may be issued to advise of such changes and or additions First Printing April 1967 Reissued March 1968 ...

Страница 3: ...Address Translation Introduction 4 4 4 5 6 6 8 8 9 9 9 10 10 12 16 Processor States 16 Processing State PI 16 Interrupt Response State P2 16 Interrupt Control State P3 16 Machine Condition State P4 16 Processor State Registers 17 Program Counter 17 General Registers 18 Floating Point Registers 18 Interrupt Status Registers 18 Interrupt Mask Registers 20 Program Mask Registers 20 Register Addressin...

Страница 4: ...dard Device Byte 0 0 0 0 0 0 0 0 65 Sense Bytes o 0 0 0 0 0 0 0 0 0 0 0 66 Channel Servicing 0 0 0 0 66 Servicing a Data Transfer 0 67 End and Chaining Servicing 0 72 Interrupt Servicing 0 0 0 0 77 Introduction 0 0 0 81 Operational Characteristics 0 0 0 81 Direct Control Interface 0 0 o 0 0 0 0 82 Static Out Lines 0 0 0 0 0 0 0 0 82 Static In Lines 0 0 0 0 0 0 0 0 82 Signal Out Line 0 0 0 0 o 0 0 ...

Страница 5: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 121 Set Program Mask SPM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 122 Introduction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123 Data Format 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123 ...

Страница 6: ...ide Decimal DP 163 Pack PACK 164 Unpack UNPK 165 Move with Offset MVO 166 LOGICAL Introduction 167 INSTRUCTIONS Data Format 167 Instruction Formats 168 Condition Code Utilization 169 Interrupt Action 169 Move MVI MVC 170 Move Numerics MVN 171 Move Zones MVZ 172 Test and Set TS 173 Compare Logical CLR CL CLI CLC 174 AND NR N NI NC 175 OR OR 0 01 OC 176 Exclusive OR XR X XI XC 177 Test Under Mask TM...

Страница 7: ...dd Normalized AER AE ADR AD 210 Add Unnormalized AUR AU AWR AW 212 Subtract Normalized SER SE SDR SD 213 Subtract Unnormalized SUR SU SWR SW 214 Compare CER CE CDR CD 215 Halve HER HDR 216 Store STE STD 217 Multiply MER ME MDR MD 218 Divide DER DE DDR DD 219 Feature 5001 46 Memory Protect 220 Feature 5002 46 Elapsed Time Clock 220 Feature 5019 46 Elapsed Time Clock 221 Feature 5003 46 Direct Contr...

Страница 8: ... Table 10 Command Code Operations 41 Table 11 Input Output Channel Registers 45 Figure 1 Data Formats Figure 2 70 46 Translation Flow Figure 3 Functional Logic of Automatic Interrupt Figure 4 Functional Logic of Program Control Instruction Figure 5 Functional Logic of Start Device Instruction Figure 6 Functional Logic of Halt Device Instruction Figure 7 Functional Logic of Test Device Instruction ...

Страница 9: ...locate a category of instructions Appendix A summarizes the instruction set for the 70 46 Processor including timing formats and condition codes ix Instruction Index Privileged Instructions _ Processor State Control Instructions _ Fixed Point Instructions _ Decimal Arithmetic Instructions _ Logical Instructions _ Branching Instructions _ Floating Point Instructions _ ...

Страница 10: ...automatic control of a job stream monitor where the presence of the user is not required The 70 46 also features an efficient technique for the handling of I O data transfer through the reduction in processing interference during I O selector channel operations and an increase in the I O transfer rate capability The Time Sharing Operating System which is used with the 70 46 Processor consists of a...

Страница 11: ...n I ILOng Floatin Point Na I I 1 7 S Character Ipacked Deci al Numbe I 31 I I I I 24 I I I I Fraction L D_i 9_i _IL D_i 9_it4 D i9 i 1 JDi9i Di9it 4 1Di9it 4 Di9i Lign 4 IZoned Decimal Number IFixed Length Logical Information I 32 Logical Data Introduction Halfword t Byte _ _ Byte _ 55156 63 56 4 it I variable Length Logical Information ICha acte 8 ICha acte 8 8 N OTE Numbers in upper right corner...

Страница 12: ... information bits The parity bit ensures the accuracy of all bytes accessed by the processor Odd parity is used in the 70 46 Processor The internal code representation in the 70 46 is either the Extended Binary Coded Decimal Interchange Code EBCDIC or the USA Standard Code for Information Interchange USASCII as specified by program See Appendices D and E There are eight distinct formats for data i...

Страница 13: ...bchannel register sets and devices can be connected to the multiplexor channel The scratch pad memory is a micromagnetic storage device consisting of 128 four byte words the cycle time of which is 300 nanoseconds Each word is scratch pad memory is uniquely addressed The following registers are contained in scratch pad memory See also Appendix 1 1 Processor Utility Registers All locations designate...

Страница 14: ...ined in the translation memory is loaded and stored from and to main memory by special EO Elementary Operation routines It is addressed during each main memory address ing cycle when translation is required Address translation does not require additional instruction time from that required by the basic 70 45 timing however staticizing time for the SS Format Load Multiple and Execute instructions i...

Страница 15: ...4 096 byte page This bit is ignored if M is reset This bit is set and reset by the program XXX bits are for future expansion and must be zeros program restriction 1 The G condition is provided as a program flag to indicate written into and or accessed respectively A first time Read or Write to a page would cause the G bit to be set 2 This translation memory is provided in addition to the 128 word ...

Страница 16: ...IT 5 PAGE CONTROL BIT CONTROL 6 BBB 24 BIT EFF ECTIVE ADDRESS OR 24 BIT VIRTUAL ADDRESS DURING FETCH OR EXECUTE Q D BIT SEGMENT 5 BITS PAGE IDISPLACEMENT 6 BITS 12 BITS INTERRUPT IF NOT B B 8 9 14 PAGE 1DECODER I PAGE ADDRESS BIT L 15 o 17 Figure 2 70 46 Translation Flow 18 BIT ACTUAL ADDRESS OF INSTRUCTION OR OPERAND t l t 1 t l t t 1 ...

Страница 17: ...terrupt is effected subject to the corresponding mask The Interval Timer runs when set to a nonzero value otherwise it does not run The decrement of the count occurs such that the total elapsed time is never less than the count set in the Interval Timer The maximum possible time interval is not greater than 100 micro seconds more than the loaded count This timer is not available to 70 35 70 45 and...

Страница 18: ...his address look up is in addition to regular staticizing time If T 1 70 46 Mode the addi tional time is required If T 0 70 45 Mode no additional time is required The contents of the general register specified by Rl is the first operand The contents of the general register specified by R2 is the second operand In floating point operations Rl designates the address of the floating point register th...

Страница 19: ... the leftmost byte of the first operand The Ll field specifies the number of additional bytes in the operand that are to the right of the first operand address To obtain the second operand address the contents of the general register specified by B2 are added to the contents of the D2 field The L2 field specifies the number of additional bytes in the operand that are to the right of the second ope...

Страница 20: ...e 2 Use of General Registers Processor State Edit and Mark P1 GR 1 P2 GR 1 Pa GR 13 P4 GR 9 Processor States are discussed on page 16 11 Instruction Formats Translate and Test GR 1 and 2 GR 1 and 2 GR 13 and 14 GR 9 and 10 ...

Страница 21: ...ot required are maintained in subsidiary storage The 70 46 programming relocates program pages dynamically within main memory so that programs are executable in different main memory locations The 70 46 basic page size is 4 096 bytes At the discretion of the program a 2 048 byte page size can also be used This shorter page length makes it possible to pack main memory more tightly as well as reduci...

Страница 22: ...48 byte pages the 11 low order bits of the displacement field are used untranslated in actual memory addresses The high order bit must be zero When the Page Control Bit is reset 4 096 byte pages the 12 bits of the displacement field are used untranslated in actual memory addresses The 11 bits of the page and segment are used to address 8 virtual segments each with 64 virtual pages The six page bit...

Страница 23: ...tion is extended The conditions which determine whether a MOVE in the 70 46 will result in an actual move or in a fill are detailed on the chart in table 2B The same rules apply to SS Logical instructions in as much as an actual move is equivalent to a valid logical result and a fill is equivalent to extending the preceding result as an operand The chart may generally be summarized in narrative fo...

Страница 24: ...tion Result Fill Move Fill Fill Move Fill Move Move Move Move Fill Move Move Table 2B Analysis of Overlapped and Non Overlapped Fields of 70 46 Move Instruction Overlapped Fields Move four byte field starting at Memory Location 1 into destination field starting at Memory Location 2 Memory Locations 2 3 4 5 Before A B C D E 1st Operation A A C D E 2nd Operation A A A D E 3rd Operation A A A A E 4th...

Страница 25: ...cessed The remaining interrupts are processed in turn depending on their priority The RCA 70 46 Processor has four processor states that provide control of system and program interrupts Programs can be executed in anyone of the states because each state is completely independent and has its own set of registers The processor states and their functions are as follows The Processing State PI interpr...

Страница 26: ...mat of the P counter is as follows Program Mask Next Instruction Address o 1 2 3 4 7 8 31 Bit Positions 0 and 1 contain the instruction length code When an interrupt occurs and is taken or a Program Control instruction is exe cuted the length of the last instruction executed in the terminated state before the interrupt condition occurred is stored in bit positions 0 and 1 as given in table 4 The i...

Страница 27: ...ed by the appropriate processor state Each time an instruction is staticized the P counter is updated to the next instruction This field is left intact whenever an interrupt requires switching to a new processor state A separate set of general registers is assigned to each processor state Each general register is 32 bits long Sixteen general registers are assigned to PI and P2 six general register...

Страница 28: ... key related to the main memory block are equal or either is zero the main memory block accepts a data store Conversely if the keys do not match and neither is zero an address error protection interrupt occurs No tes 1 If the memory protect feature is not installed this field must be zero 2 Keys are effective on actual after translation addresses Bit Position 12 designates the internal decimal cod...

Страница 29: ...essor state in which the Supervisor Call instruction is issued This code provides linkage to the program required to accomplish the purpose of the Supervisor Call instruction The Interrupt Mask register is a 32 bit register A separate register is provided for each of the four processor states Each bit in the Interrupt Mask register is associated with an interrupt condition A 0 bit in any bit posit...

Страница 30: ...lity GR Processor Utility IMR P3State GR ISR P3State GR P counter P3 State GR GR GR GR IMR P4 State GR ISR P4 State GR P counter P4 State GR Weight GR Weight 1 The P counter Interrupt Status register and Interrupt Mask reg ister for processor stc te P11 P2 and P3 can be addressed by register notation R1 R2 or R3 field of an instruction in processor state P3 only The P counter ISR and IMR for proce...

Страница 31: ...chine Check 21 P4 4 3 External Signal No 1 22 Pa 8 4 External Signal No 2 2a P3 12 5 External Signal No 3 24 Pa 16 6 External Signal No 4 25 Pa 20 7 External Signal No 5 26 Pa 24 8 External Signal No 6 27 Pa 28 9 Interval Timer 28 Pa 32 10 Selecter Channel No 1 29 Pa 36 11 Selector Channel No 2 210 Pa 40 12 Selector Channel No 3 211 Pa 44 13 Selector Channel No 4 212 Pa 48 Not used Not used 16 Mul...

Страница 32: ...eneral registers specified by the instruction also remain un changed When an instruction is terminated the condition code setting and data in the general registers and or main memory are unpredictable 2 When operating with T 0 program interrupt functions described in the 70 35 70 45 70 55 Processor Reference Manual apply When operating with T 1 program interrupt functions of table 9 apply There ar...

Страница 33: ...lways be zero when this interrupt occurs The following conditions can cause a machine check interrupt to occur Scratch Pad Memory Parity Error This error can occur when data is read from the Scratch Pad Memory Main Memory or Non Addressable Main Memory Parity Error If a main memory parity error occurs during an I O data transfer this interrupt condition does not occur A channel interrupt occurs an...

Страница 34: ...upts cause termination of the instruction with unpredictable results Translation Table Location contains an element with control bit U 0 i e page cannot be used and memory is addressed via address translation D 0 and T 1 This interrupt causes the instruction to be suppressed Note This interrupt may occur on instruction staticizing or operand fetching The interrupt occurs such that the instruction ...

Страница 35: ... P counter of the terminated state tells how far to rollback the P count to reach its value prior to interrupt as follows ILC 01 10 11 Length in Bytes Two bytes back Four bytes back Six bytes back Note The ILC is always generated from the operation code of the instruction Three conditions cause an address error interrupt to occur They are address error specification error and protection error Addr...

Страница 36: ...halfword boundary The operation is suppressed P1 otection An address error protection interrupt occurs when the storage key and the protection key of the result main memory location do not match and neither is zero The operation is suppressed if the first main memory location specified that the instruction is in a protected area The operation is terminated with unpredictable results if the instruc...

Страница 37: ...sk the operation is completed the exponent is unaltered and the interrupt is taken If the interrupt is inhibited by the program mask the interrupt condition is cancelled and the operation is completed by setting the result to true zero zero sign zero exponent and zero mantissa If the interrupt is permitted by the program mask but inhibited by the interrupt mask the interrupt remains pending and th...

Страница 38: ...rrupt is inhibited by the program mask the interrupt condition is cancelled If the interrupt is permitted by the program mask but inhibited by the interrupt mask the interrupt remains pending 231 This interrupt provides program control over the processor during program testing The program test interrupt flag is set by the Program Control instruction When the interrupt flag bit and the related inte...

Страница 39: ...te Is it Power Failure Machine Check Interrupt or Scratch Pad Memory parity error if applicable No Initiate P3 Reset Flag in Interrupt Flag Register 7 8 10 1 Extract CC and Program Mask from P Counter of Initiated State Figure 3 Functional Logic of Automatic Interrupt 30 No Program Interrupt Hold Interrupt Pending and Continue at Next Instruction Yes Initiate P 4 Reset Flag in Interrupt Flag Regis...

Страница 40: ...ted State 13 I Store Weight of Interrupt in GR No 15 of Initiated State See Note 4 14 Supervisor Call Interrupt Yes I 15 Store Call in ISR of State in No which the Supervisor call was executed 16 Static ize and Execute instruction specified by P Counter of Initiated State Interrupt Analys is Program Figure 3 Functional Logic of Automatic Interrupt Cont d 31 ...

Страница 41: ...register is set the interrupt is taken and information OLC CC program mask is stored in the P counter of the state being terminated Blocks 6 and 7 If the interrupt condition is a power failure a machine check or Scratch Pad Memory parity if applicable the Machine Condition State P4 is initiated The flag in the Interrupt Flag register is reset Block 8 If the interrupt is a Machine Check the Program...

Страница 42: ...instruction is set Block 3 Block 4 Block 5 Block 6 Block 7 If the program test bit is not set the Interrupt Mask register for the state to be initiated by the Program Control instruction is compared to the Interrupt Flag register If an interrupt condition has occurred the events described under automatic interrupt take place see figure 3 block 3 Important If an interrupt is outstanding in the stat...

Страница 43: ...r of Term inated State Store ILC CC and Program Mask in P Counter of Terminated State Program Test Bit in Program Control Instruction Set 3 4 5 6 7 Program Interrupt No Compare IFR to IMR of State to be initi ated by Program Control Instruction No Interrupts Outstanding Initiate State Specified in Program Control Instruction Extract CC and Program Mas k from P Counter of Initiated State Extract Ke...

Страница 44: ...her USASCII or EBCDIC as specified by bit 12 in the Interrupt Status register When an automatic interrupt occurs or a Program Control instruction is executed the decimal mode is not stored in the Interrupt Status register of the terminated state The mode of the state being initiated is determined by the mode bit in its own Interrupt Status register Consequently to change mode the mode bit of the I...

Страница 45: ...tor channels and a multiplexor channel Up to four selector channels optional can be attached to a 70 46 Processor each selector channel can address up to 256 peripheral devices Provision is made for up to four high speed selector channels as options on the 70 46 Processor The high speed selector channels reduce main memory interference due to input output data transfers such that the maximum aggre...

Страница 46: ...ctor channel and the peripheral device one byte at a time The multiplexor channel is standard on the 70 46 Processor and can address up to 256 devices The multiplexor channel has eight standard interface trunks each of which can be connected to a device control electronics This permits the multiplexor channel to operate devices on all eight trunks simultaneously The limit as to the number of input...

Страница 47: ... Start Device instruction or by manually pressing the LOAD pushbutton indicator on the Model 70 97 Console Execution of the Start Device instruction causes the information contained in the Channel Address Word CAW Channel Block Address CBA and the Channel Command Word CCW to be transferred to the input output channel registers in scratch pad memory for the specified selector channel If the specifi...

Страница 48: ...cing is required and the input output device is serviced After a device is serviced processing resumes or another device is serviced Each selector channel and the multiplexor channel has a scanning priority If servicing is required by devices on more than one channel the channel with the highest priority is serviced first The priority is as follows Selector Channel No 1 Selector Channel No 2 Selec...

Страница 49: ... the initial channel command word The Channel Block Address CBA is used by the Start Device instruc tion see Privileged Instructions Section and specifies that the Start Device Operation was initiated CC 0 In this event the contents of the CBA are loaded into the selector channel registers as follows Selector No 1 2 3 4 Scratch Pad Word Address 36 66 76 A6 If mUltiplexing the contents of the CBA a...

Страница 50: ...mmand is issued to a card reader the command after being accepted is terminated by the device con trol electronics A channel interrupt occurs and the sense byte s indicate the illegal operation 2 The bit position designated as B indicates that the specified device is connected to the multiplexor channel and the multiplexor is to be operated in the burst mode If this position is a 1 bit the multi p...

Страница 51: ...ice control electronics The device control electronics interprets this information as control information and initiates a function not involving a data transfer The address specified by the CCW is the leftmost main memory location of the output area Transfer in Channel 10 01 This command provides chaining of CCW s that are not located in adjacent double word main memory An actual branch to the add...

Страница 52: ...device by executing one Start Device instruction When command chaining is specified by setting this bit a chain series of channel command words in sequence is used and each channel command word specifies the operation to be performed When the operation specified by one channel command word is completed the next channel command word in sequence is automatically fetched and the operation specified i...

Страница 53: ...d by this command is suppressed This bit can be used only with Read Read Reverse or Sense commands 4 Bit position 36 is the Program Controlled Interrupt flag PCl During data and command chaining the 70 46 Processor has the ability to notify the program of the progress of chaining through an interrupt when a channel command word is fetched When this bit is set a channel interrupt occurs when the ch...

Страница 54: ...ry Memory Main Memory Channel Address 1 per selector 1 per multiplexor 1 per device Register CAR channel channel Channel Command 1 per selector 1 per multiplexor 1 per device Register I CCR I channel channel Channel Command 1 per selector 1 per multiplexor 1 per device Register II CCR II channel channel Assembly Status 1 per selector 1 per mUltiplexor None Register channel channel CBA Register 1 p...

Страница 55: ...can range from 0 bytes to 65 536 bytes When the I O is terminated these bit positions contain the remaining byte count if any Command Data Address of First Byte or Location of new CCW 0000 Code if Command is Transfer in Channel o 3 4 7 8 31 Bit Positions 0 through 3 are used by the processor It should be noted that these bits are used in the channel command word as modifier bits Once the command h...

Страница 56: ...sults in the form of condition codes are available upon instruction com pletion It should be noted that the condition code settings indicate the results of the instruction and not the results of the input output operation that the instruction may be initiating The channel continues off line to accomplish the input output operation as specified by the instruction However during this time the proces...

Страница 57: ...l On System Yes Is Specified Channel 1 Busy Selector 2 Selector with Interrupt Pending 3 Multiplexor In aurst No Reset the Channel Status Byte and the Standard Device Byte to Zero If the Memory Protect Feature is Not Installed Is Key in CAW O Yes Is Main Memory Address in CAW on a Double Word Boundary Yes Is Main Memory Address in CCW in Avai lable Main Memory Yes Yes Input Output Operation Set Co...

Страница 58: ... Command to Specified Device Control Electronics Receive Standard Device Byte from Device and Set Condition Code 9 No Is the Condition NO Is there a Pending Channel Interrupt Yes Set Condition Code to 2 and Terminate Start Device Instruction Next Instruction I O Operation Not Initiated Code Set to O r Yes Is the Specified Channel the Multiplexor No Transfer CAW and CCW to Appropriate Selector Chan...

Страница 59: ...nel CO mmand WO rd CCW is tested to see if it is within the available main memory for the system If it is not the prO gram check bit in the channel status byte is set the condi tion code is set to 1 the Start Device instruction is terminated and program control is transferred to the next instruction The input output operation is not initiated Block 8 If the specified channel is the multiplexor cha...

Страница 60: ... Sense the condition code is set to 0 permitting the operation to be initiated A test is made to see if the condition code is set to 0 input output operation can be initiated If the condition code is zero a test is made to see if the specified chan nel is the multiplexor channel If the specified channel is a selector channel the Channel Address Word and Channel Block Address if T 1 are fetched fro...

Страница 61: ...nnel registers and the command is sent to the device The legality of the command is not determined at initiation time If the device gets an illegal command the operation is terminated and a channel interrupt occurs The standard device byte stored in the appropriate channel registers when the interrupt is taken indicates a secondary indicator A Sense command must be issued to bring the Sense byte s...

Страница 62: ... see Chaining and End Servicing section below If the specified channel is not the multiplexor channel the condition code is set to 0 the Halt Device instruction is terminated and program control is transferred to the next instruction If the specified channel is the multiplexor channel the channel status byte and the standard device byte are reset to zeros in the mUltiplexor channel registers The d...

Страница 63: ... 1 Busy Selector Channel 2 Multiplexor Channel in Burst No Is Specified Channel the Multiplexor Yes Reset the Channel Status Byte and the Standard Device Byte to Zero Send Device Address to All Trunks on Multiplexor Channel No Yes Input Output Operation Tell Devi ce to Set an End Condition Reset Chain Command CC Flag in CCR II in Scratch Pad Memory Set Condition Code to 2 and Terminate Halt Device...

Страница 64: ...Receive Standard Device t Byte from Device Next Instruction 1 Store Standard Devi ce Byte in Multiplexor Channel Registers in SPM 1 Tell Device to Set an End Condition I Reset Chain Command CC Flag in CCR II in Non Addressable Main Memory 9 I Terminate Halt Device Instruction Next Instruction Figure 6 Functional Logic of Halt Device Instruction Cont d 55 ...

Страница 65: ...nstruction is terminated Both the channel number and the device number must be specified in the instruction Because the Channel Address Word is not referred to by the Test Device instruction the Channel Address Word Channel Block Address and a Channel Command Word are not required Upon execution of a Test Device instruction the following events occur see figure 7 Block 1 If the privileged mode bit...

Страница 66: ...s on Specified Channel No Is the Specified 1 Device Control Electronics Set Condition Code to 3 ond Terminate Test Device Instruction Next Instruction 7 8 9 Operable Receive Standard Device Byte from Devi ce and Set Condition Code Is the Condition Code Set to 1 No Terminate Test Device Instruction Next Instruction Yes Yes Figure 1 Functional Logic of Test Device Instruction 57 Input Output Operati...

Страница 67: ...pecified device is busy but the device control electronics is not busy i e tape rewinding off line seek 1 The specified device is inoperable 0 The specified device and control electronics is available Block 8 A test is made to see if the c onditi on code is set t o 1 If it is the standard device byte is transferred t o the channel registers f or the channel specified the Test Device instructi on i...

Страница 68: ...it Set to Zero Yes Is Specified Selector Channel on System Is Specified Channel 1 Busy Sel ector 2 Selector with Interrupt Pending 3 Multiplexor in Burst No No Set Condition Code to 0 and Terminate Check Channel Instruction Next Instruction Yes Figure 8 Functional Logic of Check Channel Instruction 59 Input Output Opera tim Set Condition Code to 2 and Terminate Check Channel Instruction Next Instr...

Страница 69: ...mination interrupt pending or if the specified channel is the multiplexor that is operating in the burst mode the condition code is set to 2 the Check Channel instruction is terminated and program control is trans ferred to the next instruction Block 4 If the specified channel is a selector channel that has an external device request interrupt pending the condition code is set to 1 the Check Chann...

Страница 70: ...conditions 1 A parity error occurs while accessing the Channel Address Word Channel Block Address or a Channel Command Word The channel control check bit in the channel status byte is set 2 The Memory Protect feature is not installed and the key in the CAW is not zero The program check bit in the channel status byte is set 3 The main memory address specified in the CAW is not on a double word boun...

Страница 71: ...ector channel or the multiplexor channel operat ing in burst mode is specified and it is not busy No termination is required 3 The multiplexor channel is specified and the addressed device control electronics has a termination interrupt pending No termination is required This condition code indicates that the specified device is on the multiplexor channel and that the standard device byte has been...

Страница 72: ...sy 2 A selector channel is specified that has an interrupt pending termination or external device request 3 The multiplexor channel is specified and it is operating in burst mode 4 The multiplexor channel is specified and the addressed device control electronics is busy with addressed or non addressed device 5 The multiplexor channel is specified and the addressed device control electronics has a ...

Страница 73: ...not com pletely filled by transmission from the device The final byte count in Channel Command Register II is greater than zero 2 Count High on Output Write Write Control Data in the main memory area specified by the Channel Command Word is not com pletely transferred and the device terminated The final byte count in Channel Command Register II is greater than zero Notes 1 If incorrect length occu...

Страница 74: ...aced with the systems error byte hexadecimal FF and the input output operation is completed For parity error characters going to a device writing the invalid character is transferred unchanged the operation is terminated and a channel interrupt occurs for the specified channel The transfer of sense byte s to memory is not checked for parity Bit Position 13 is the channel control check bit When set...

Страница 75: ...tion 81 is the status modifier bit This bit is used with Command chaining When set this bit indicates that the next Channel Command Word is skipped This bit is set as a result of device termination The sense byte or bytes are brought into main memory from an input output device by using the Sense com mand These bytes contain status information for the device referred to The exact status informatio...

Страница 76: ...nel is operating in the multi plexor mode This occurs at the conclusion of the burst operation when the last data byte has been serviced prior to interrupt Servicing of a data transfer causes the following events to occur see figure 9 If the service request comes from a device control electronics con nected to the mUltiplexor channel which is operating in the multiplex mode the processor gets the ...

Страница 77: ...lag in the Command Set r No 5 No 6 Yes 7 Has Device Indicated an End Condition No Decrement the Byte Count by One Is the Command A Read Yes Is the Skip Flag in the Command Set No Is the Command a Sense Yes Input Output Operation Get Devi ce Addre and Fetch Subchannel Registe I O Service Request for Multiplexor in Burst Mode Yes Go to End and t Chaining Servicing Block 1 Figure 9 Functional Logic o...

Страница 78: ... Instruction Input Output Operation ________ ________ 8 Set Channel Data Check Bit in Channel Status Byte Change Data Byte to FF 16 ________________ 10 Decrement the Main Memory Data Address By One Is the Chain Data CD Flag in the Cammand Set 13 Ha Tell Device to Set an End Condition Go to End and Chaining Servicing _ Block II Figure 9 Functional Logic of Servicing a Data Transfer Cont d 69 ...

Страница 79: ... Control is then transferred to Block 11 If the command is a read a test is made to see if the SKIP flag is set If it is transfer of the data byte to main memory is bypassed and control is transferred to Block 10 If the SKIP flag is not set a test is made to see if the command is a Sense If it is parity checking of the data byte is bypassed and control is transferred to Block 9 If the command is n...

Страница 80: ...e is to be trans ferred is tested to see if it is in available main memory for the system If it is not the program check bit in the channel status byte is set no data transfer occurs and the device control electronics is told to set an end condition on the next data service request see Block 13 3 The following tests occur when a data byte is transferred from main memory a The main memory address f...

Страница 81: ...pecifies command chaining the CC flag in the command is set this service is used to fetch the next com mand in the chain and to send this new command to the input output device 2 If the current command specifies data chaining the CD flag in the command is set this service is used to fetch the next command in the chain so that the current operation can be continued End and Chaining Servicing causes...

Страница 82: ... the standard device byte is tested to see that the following conditions are present Device is operable Secondary indicator is not set Device end is set If any of the above conditions is not present control is transferred to Block 8 which causes termination of the command and suppression of command chaining to occur If all of the conditions tested in the standard device byte are present a test is ...

Страница 83: ... Control Electronics to Set Channel Interrupt Is This a Multiplexor Channel Device Ves Store Subchannel Registers Back in Non Addressable Main Memory Next Instruction Ves S Ves 6 No 7 Ves Test Channel Status Byte for Program Check Pro tection Check Data Check or Channel Control Check No Is the Chain Data CD Flag Set No Test Standard Device Byte for the Following Device Inoperable No Secondary Ind ...

Страница 84: ...er in Channel Command on a Double Word Boundary 17 No Yes 16 Transfer Main Memory Address in Transfer in Channel Command in Next CCW Address Send Command to Specified Devic e 1 ____________ No Data Chain Set Program Check Bit in Channel Status Byte 14 __ __ Is this a Burst Mode Operation 14 No Stare Subchonnel Registers back in Non Addressable Main Memory Yes Yes See Note 4 Is this a Multiplexor C...

Страница 85: ...mented by eight Block 12 A test is made to see if the next command in sequence is a Transfer in Channel command Block 13 If the command is not a Transfer in Channel command a test is made to see if this is a command chain or a data chain operation If it is a com mand chain operation the new command is sent to the specified device con trol electronics This is not required if this is a data chain op...

Страница 86: ... electronics is told to set a channel interrupt condition see Block 8 3 If a scratch pad memory parity error occurs when storing the sub channel registers back in non addressable main memory the chan nel control check bit in the channel status byte is set 4 If a scratch pad memory parity error occurs when storing the sub channel registers back in non addressable main memory the chan nel control ch...

Страница 87: ... _ _ _ _ _ _ _ _ _ J See Note 2 5 No 6 7 8 No Is This a Termination Interrupt Yes Set Termination Interrupt Bit in Channel Status Byte Test for Incorrect Length No Store Standard Device Byte in Appropriate Registers in Scratch Pad Memory If Required t Next Instruction No 2 Yes 8 Input Output Operation Generate an All Z ro Standard Devi ce Byte and Store it into 1 0 Channel Registers in Scratch Pad...

Страница 88: ...t This interrupt occurs when an input output operation initiated by the processor has terminated When this interrupt occurs the standard device byte and the subchannel registers if a multi plexor device are stored in the appropriate input output channel registers This is the final servicing of the channel and device At the completion of this servicing the channel is free to accept another operatio...

Страница 89: ...e to see if the byte count is not equal to zero and the Suppress Length Indicator SLI flag is equal to zero If these conditions are present the program desires an indication of incorrect length and the incorrect length bit in the channel status byte is set Block 8 The standard device byte is stored in the appropriate input output channel registers and program control continues with the next instru...

Страница 90: ...om the out line of one processor to the in line of a second processor in a multi processor installation by means of the Direct Control feature provides 256 code combinations The code sets can be any required by the program including EBCDIC and USASCII with code interpretation being performed by the program When a transmitting processor issues a Write Direct instruction an external interrupt is set...

Страница 91: ...ay be uniquely sampled by a Read Direct instruction which specifies the desired trunk See Read Direct instruction The Signal Out line provides a signal to the other processors upon execution of a Write Direct instruction The Direct Control Trunks DCT whose Signal Out lines are signaled is specified by the I Field pattern of the instruction The External Signal In line provides the means for receivi...

Страница 92: ...2 Multi Processor Installation The following illustration is presented to demonstrate the manner in which two processors are interconnected In this instance only one cable is required PROCESSOR 2 TI STA C OUT STATIC IN SIGNA LOUT EXT SIGNAL IN PFNo P FIR WRIT E OUT HO Lo IN CABLE CONNECTS TO OCT 1 Figure 12 Dual Processor Complex 83 ...

Страница 93: ... cannot communicate with each other The following illustration demonstrates the manner in which the master processor interconnects with up to five satellite processors via the Direct Control Trunks DCT DCTt DCT2 IDCTl SATELLITE PROCESSOR 2 IDCTt SATELLITE PROCESSOR 3 IDCT1 SATELLI TE PROCESSOR 4 MASTER PROCESSOR 1 DCT3 DCT4 DCT5 Figure 13 Master Satellite Complex 84 DCT6 DCTI I SATELLITE PROCESSOR...

Страница 94: ...CT5 oCTS Multi Processor InB tallation The following illustration demonstrates the manner in which six proces sors may be interconnected so that any two processors may communicate oCTl oCT2 oCT3 PROCESSOR oCT4 4 oCT5 oCTS oCT1 oCT2 oCT3 PROCESSOR 5 oCT4 oCT5 oCTS OCTl oCT2 oCT3 PROCESSOR oCT4 S oCT5 oCTS Figure 14 Maximum Multi Processor Complex 85 ...

Страница 95: ... Interrupt Weight is used to branch to the Supervisor Call routine where the Supervisor Call Interrupt Code is decoded and a branch is made to the required routine in this case the Write Direct routine The Write Direct routine then performs the following 1 Checks to determine whether Write Direct instruction can be issued or must be stacked in queue 2 Fetches the user parameters 3 Sets Write Direc...

Страница 96: ...Power Failure code all zeros is received the processor that is down is removed from the system configuration and a return to normal processing is effected For all other codes received a Write Direct acknowledgement is issued as follows 1 Supervisor Call is issued with a Write Direct Interrupt Code 2 A Write Direct instruction with a Data Byte of an Acknowledge Code and a return address of the user...

Страница 97: ... Direct the Read Direct instructions and all input output instructions The first address BdD1 specifies the main memory location of the first operand The second operand js the immediate byte in the 12 field I Op Code I L Bl o 7 8 15 16 19 20 31 32 35 36 47 Description The SS format is used by the Load Scratch Pad and the Store Scratch Pad instructions The location of the first operand is specified...

Страница 98: ...pt occurs when the storage key and the protec tion key of the result location do not match The operation is terminated The result data is unpredictable This interrupt can occur only if the memory protect feature is installed A privileged operation interrupt occurs if execution of any privileged instruction is attempted and the non privileged mode bit bit position 15 in the Interrupt Status registe...

Страница 99: ... the 24 bit is zero are available for Special Functions This instruction is only incorporated on the 70 46 Processor The routine specified by the I field must be incorpo rated in the ROM Otherwise an Op Code Trap Interrupt condi tion occurs 2 This instruction is available to 70 46 programs only If it is executed in the 70 45 mode an Op Code Trap Interrupt condition occurs 3 If a location outside t...

Страница 100: ...onditions the indicated interrupt results S Bit N Bit D Bit Interrupt N A 1 1 Paging Error 0 1 0 Paging Error 1 1 0 Privileged Operation N A Not applicable 5 If this instruction is attempted in a non utilizable page a Paging Queue Interrupt condition occurs and the instruction is suppressed 91 ...

Страница 101: ... Unchanged Interrupt Action Addressing Power Failure Machine Check Paging Error Paging Queue Notes 1 The high order byte of the general register specified by R1 contains a count of 0 255 to specify 1 256 translation memory locations in each of the blocks 2 The low order three bytes of the general register specified by R1 containing the address of the Block A ddress Table may be either virtual or d...

Страница 102: ...om which the trans lation memory entry is copied is WGUSEMXXXPPPPPPH 10 The format of the translation memory entry is specified under the Translation Memory description in this manual 11 If the block address specified in Block Address Table entry is not on a halfword boundary an Addressing Interrupt condition occurs The operation is terminated with unpredictable results 12 If this Special Function...

Страница 103: ...ough 15 in the general register specified by R2 contain the address 0 511 of the first translation memory location to be loaded This may specify any location in the translation memory Bit positions 0 through 6 are not used and must be zeros This is a program restriction only 4 Bit positions 23 through 31 in the general register specified by R2 contain a count 0 511 specifying the number of words i...

Страница 104: ...redictable results a If either the address of the Block Address Table or the block address in a Block Address Table entry specifies a nonexistent translation nlemory element i e the two unused bits of the segment field of a virtual address are not zeros b If either the address of the Block Address Table or the block address in a Block Address Table entry specifies a 2 048 byte page in the high ord...

Страница 105: ... is specified an Address Interrupt condition occurs The operation is suppressed with the operands unchanged 4 If a location outside the available memory is addressed an Address ing Error Interrupt condition occurs The operation is terminated with unpredictable results 5 The contents of the translation memory being stored into memory do not cause a Paging Queue condition or Paging Error Interrupt c...

Страница 106: ...n 02 Format Base Displacement Condition Code Interrupt Action Notes 0 3 4 Unchanged Address Error Power Failure Machine Check Paging Error Paging Queue 15 1 If either this Special Function or the timer halfword addresses are not on halfword boundaries an Addressing Error Interrupt condi tion occurs 2 If the counter is reset to zero after zero occurs and the interrupt flag has been set the interrup...

Страница 107: ... Address Error Power Failure Machine Check Paging Error Paging Queue 15 Note 1 If either this Special Function or the timer halfword addresses are not on halfword boundaries an Addressing Error Interrupt condi tion occurs 2 Use of the Interval Timer and Diagnostic Snapshot by programs may not occur together since the counter register is common to both If the Diagnose function is initiated while th...

Страница 108: ...d to analyze those interrupts that can occur during staticizing or execution The NIA field of the object P counter and the ILC are set correctly to permit this Special Function to back up the object P counter for reentry to the object instruction following completion of the page calling 2 An index is provided in General Purpose Register 15 of the current state This index is the number of virtual a...

Страница 109: ... Flags the stack address as a Direct Address not subject to translation If multiple interrupt conditions of different kinds occur on the same page the page address is listed once in the address stack and all applicable condition bits are set 5 This Special Function is to be used for analysis of Paging Error condition or Paging Queue Interrupt condition on the normal instruc tion set of the 70 46 a...

Страница 110: ...ue may have occurred and the ending source field address pro vided by this Special Function may not be correct 9 When a Paging Error or Paging Queue Interrupt occurs the Pro gram Counter Interrupt Status Register and General Purpose Registers of the Interrupted State must not be altered before the special function is executed 10 This Special Function should be used only if a Paging Queue con ditio...

Страница 111: ... Address error Addressing Specification 1 The L field provides an eight bit count specifying the number of scratch pad memory locations to be loaded An initial count of zero specifies one word to be loaded 2 The first address specifies scratch pad memory words 0 through 127 by the seven rightmost bits of the address The bits to the left of the seven bit address must be zero 3 The second address mu...

Страница 112: ...19 20 Unchanged Privileged operation Address error Addressing Specification Protection D2 31 32 35 36 47 Notes 1 The L field provides an eight bit count specifying the number of scratch pad memory locations to be stored An initial count of zero specifies one word to be stored 2 The first address specifies scratch pad memory words 0 through 127 by the seven rightmost bits of the address The bits to...

Страница 113: ...tiated state is then used to set the condition code indicators Privileged operation Address error Addressing 1 The immediate byte in the 12 field of the instruction is divided into four subfields as follows 8 9 10 11 12 13 14 15 _ r I V _ _ J1 v Unused Program Test Bit Direct State Initiation Indirect Control Flag Bits 8 through 10 are unused The three bit unused portion must be zero Bit 11 is the...

Страница 114: ... Note The leftmost bit of the three bit direct state initiation field must be zero This is a programming restriction Bit 15 is the indirect control flag bit If indirect state control is specified bit 15 1 the three bit direct state initiation field is ignored The three bit interrupted state identifier lSI which indicates the last state inter rupted specifies the state to be initiated This informat...

Страница 115: ... with the I field zero the Idle light of the console is on 2 Any interrupt occurring while the idle mode is in effect is taken if permitted via the Interrupt Mask register 3 The Bl and Dl fields of this instruction must be zero 4 For normal programming the I field must be zero For maintenance programming bits within the I field have the following meaning Bit 15 I set alarm inhibit Bit 14 I reset a...

Страница 116: ...mechanics of this instruction are implemented specifically for the 70 46 Processor 83 o 7 8 15 16 19 20 31 Note Use of the Interval Timer and Diagnostic Snapshot by programs may not occur together since the counter register is common to both If the Diagnose function is initiated while the Interval Timer is running the shared counter is cleared to zero without occurrence of the Interval Timer Inter...

Страница 117: ...5 16 19 20 31 0 input output operation initiated and channel proceeding with execution 1 status bits stored in scratch pad memory 2 busy or interrupt pending 3 inoperable For a detailed description of the condition code settings see Notes below Privileged operation 1 The address portion of this instruction specifies the device and channel as follows Bit Positions Channel Specified 21 22 23 0 0 0 M...

Страница 118: ...exor chan nel indicates that a device request interrupt pending condition is present The external device request interrupt pending bit in the standard device byte is set b The Start Device instruction specifies a command which is other than a Sense command and the addressed device is inoperable The device inoperable bit in the standard device byte is set c The specified device is busy but the devi...

Страница 119: ...n has been initiated do not cause a machine check interrupt A channel interrupt occurs and the program is notified of the error via the channel status byte 10 If the first CCW is a Transfer in Channel command the Start Device instruction terminates and the condition code is set to o However the specified device control electronics recognizes this command as an illegal operation and causes a channe...

Страница 120: ...e condition code settings see Notes below Privileged operation 1 The address portion of this instruction specifies the device and channel as follows Bit Positions Chann 1 Specified 21 22 23 0 0 0 Multiplexor 0 0 1 Selector No 1 0 1 0 Selector No 2 0 1 1 Selector No 3 1 0 0 Selector No 4 1 1 0 Undesignated Bit positions 24 through 31 specify one of 256 possible devices 2 If a device operating on a ...

Страница 121: ...byte is never stored The standard device byte is stored under the following conditions a The specified device indicates that a device request interrupt pend ing condition is present The external device request interrupt pending bit in the standard device byte is set b The specified device is busy but the device control electronics is not busy i e tape rewinding The device busy bit in the stand ard...

Страница 122: ... channel as follows Bit Positions Channel Specified 21 22 23 0 0 0 Multiplexor 0 0 1 Selector No 1 0 1 0 Selector No 2 0 1 1 Selector No 3 1 0 0 Selector No 4 1 1 0 Undesignated Bit positions 24 through 31 specify one of 256 possible devices 2 The channel address word in main memory location 72 the channel block address in main memory 76 and the channel command word are not used by this instructio...

Страница 123: ...he standard device byte is set 6 Condition Code 2 is set under the following conditions a A selector channel is specified that is busy b A selector channel is specified that has an interrupt pending termination or external device request c The multiplexor channel is specified and it is operating in burst mode d The multiplexor channel is specified and the addressed device control electronics is bu...

Страница 124: ...interrupt pending b The specified multiplexor is operating in the burst mode 3 A selector channel is specified that is not in the system Privileged operation 1 The address portion of this instruction specifies the channel to be tested as follows Bit Positions Channel Specified 21 22 23 0 0 0 Multiplexor 0 0 1 Selector No 1 0 1 0 Selector No 2 0 1 1 Selector No 3 1 0 0 Selector No 4 1 1 0 Undesigna...

Страница 125: ...rough 27 are ignored Bits 28 through 31 must be zero 0 0 0 2 When the five bit storage key is inserted into bits 24 through 28 of the general register specified by the first address bits 0 through 23 are unaltered and bits 29 through 31 are made zero 3 The address of the storage key for a specific 2 048 byte main memory block is specified in R2 by a binary count as shown in the following examples ...

Страница 126: ...n code trap if the memory protect feature is not installed 1 Bits 8 through 20 of the register specified by the second address R2 contain the location of the 2 048 byte main memory block where storage key is to be set Bits 0 through 7 and 21 through 27 are ignored Bits 28 through 31 must be zero 2 Bits 24 through 28 of the general register specified by the first address R1 contain the five bit sto...

Страница 127: ...g to the following pattern I Fiel4 Trunk s Pulsed Bit to 1 Six Bit 1 1 Five Bit 2 1 Four Bit 3 1 Three Bit 4 1 Two Bit 5 1 One Bit 6 0 Reserved Must be zero Bit 7 0 Reserved Must be zero More than one I Field bit may be set to 1 providing pulses for sending over more than one direct control trunk This permits sending the same byte to all processors connected to the trans mitting processor 2 A proc...

Страница 128: ... Each of the six Direct Control trunks has a set of Direct In lines which are sampled according to the following pattern I Field Trunk Sampled Bit 0 1 Six Bit 1 1 Five Bit 2 1 Four Bit 3 1 Three Bit 4 1 Two Bit 5 1 One Bit 6 0 Unused Must be zero Bit 7 0 Unused Must be zero The program must specify only one I Field bit set to 1 otherwise results of the instruction are unpredictable 2 A processor c...

Страница 129: ...tate in which the system is operating to be set to the value specified by the instruction This instruction always changes the condition code OpC e o 7 8 11 12 15 The RR format is used for the Supervisor Call and Set Program Mask instructions For the Set Program Mask instruction the R2 field is ignored The contents of the general register specified by the Rl field form the first operand For the Sup...

Страница 130: ...n is issued The supervisor call interrupt flag bit priority 21 is set in the Interrupt Flag register and a program interrupt may occur depending on the associated mask bit in the Interrupt Mask register of the current state o 7 8 11 12 15 Unchanged None If a higher priority interrupt is honored upon executing this instruc tion the flag bit priority 21 will be set and the Supervisor Call byte store...

Страница 131: ...g to bits 2 and 3 of the general register specified by Rl as follows Condition Code Setting 2 3 Result 0 0 Set condition code 0 zero 0 1 Set condition code 1 1 0 Set condition code 2 1 1 Set condition code 3 The program mask is set according to bits 4 7 of the general register specified by Rl as follows Program Mask Setting Bit Result 4 Fixed point overflow 5 Decimal overflow 6 Exponent underflow ...

Страница 132: ...t integer field is used by some shift multiply and divide instructions A pair of adjacent registers addressed by the even address of the leftmost register contains these longer operands The sign bit of the rightmost register becomes part of the integer field The same register can be specified for both operands in register to register operations except for the Divide instructions In main memory fix...

Страница 133: ...of the product of two maximum negative numbers is a double length positive number An overflow carries into the leftmost bit which is the sign and changes it In algebraic shifting however the sign bit is unchanged even when significant bits in a shift left instruction are shifted out The following three formats RS RX RR are used for fixed point operations o 7 8 11 12 15 16 19 20 31 Description An a...

Страница 134: ...a zero less than zero or greater than zero result Condition Code 3 is set for overflow result In comparison instructions the Condition Codes 0 1 or 2 indicate that the first operand is equal to less than or greater than the second operand In add and subtract logical instructions the Condition Codes 2 and 3 indicate either a zero or non zero result with a carry from the sign bit The Condition Codes...

Страница 135: ...ration is suppressed and the condition code and data in the registers and main memory are unaltered The only exception is the Store Multiple instruction which is terminated The amount of data stored is unpredictable This interrupt can only occur if the memory protect feature is installed Data Error A data error interrupt occurs when an invalid digit or sign code of the decimal operand is encount e...

Страница 136: ...ddress R2 or XzlB2 D2 is loaded into the general register specified by the first address R1 I LR 18 Rl R2 0 7 8 11 12 I L 58 Rl X2 0 7 8 11 12 Unchanged Address error Addressing RX format Specification RX format 15 B2 15 16 19 20 31 Note The operand in the register or main memory location specified by the second address remains unchanged 127 ...

Страница 137: ... into the general register specified by the first address R1 o 7 8 11 12 15 16 19 20 31 Unchanged Address error Addressing Specification Notes 1 When the halfword second operand is fetched from main memory it is expanded to a full word by propagating the sign bit value through the 16 high order positions of the receiving register 2 The operand specified by the second address is unaltered 128 ...

Страница 138: ...fied by the first address R1 The condition code is determined by the magnitUde and the sign of the loaded operand o 7 8 11 12 15 0 result is zero 1 result is less than zero 2 result is greater than zero 3 not used None 1 The same register can be specified for both Rl and R2 If this is done the operation is equivalent to a test with no data movement 2 The operand specified by the second address R2 ...

Страница 139: ... the first address R1 The condition code is determined by the magnitude and the sign of the loaded operand o 7 8 11 12 15 0 result is zero 1 result is less than zero 2 result is greater than zero 3 overflow Fixed point overflow 1 Zero operands remain constant and unchanged under complementa tion 2 A fixed point overflow interrupt occurs when the maximum negative number is complemented 3 The operan...

Страница 140: ...ress R1 In loading the absolute value of the operand nega tive numbers are complemented and positive numbers remain unaltered The magnitude of the absolute value determines the condition code 10 Rl R2 0 7 8 11 12 16 o result is zero 1 not used 2 result greater than zero 3 overflow on complement Fixed point overflow 1 A fixed point overflow interrupt exists if a maximum negative num ber is compleme...

Страница 141: ...l register specified by the first address R1 In loading the operand value positive numbers are complemented and negative numbers remain unaltered The magnitude of the loaded value determines the condition code setting o 7 8 11 12 15 0 result is zero 1 result is less than zero 2 not used 3 not used None 1 A zero operand is not altered and retains a positive sign 2 The operand specified by the secon...

Страница 142: ...ded Loading of the general registers continues in the ascending order of their addresses beginning with the register specified by RI As many words as needed are fetched from the main memory location specified continuing up to and including the register specified by Ra o 7 8 11 12 15 16 19 20 31 Unchanged Address error Addressing Specification 1 If Rl and Ra specify the same register only one word ...

Страница 143: ... 12 0 sum is zero 1 sum is less than zero 2 sum is greater than zero 3 overflow Fixed point overflow Address error Addressing RX format Specification RX format 15 B2 15 16 19 20 31 1 All 32 bits of both operands participate in the addition If the carries into and out of the sign bit disagree an overflow exists The overflow does not alter the sign bit created by the carries 2 A negative overflow re...

Страница 144: ... overflow Fixed point overflow Address error Addressing Specification 1 The halfword in main memory specified by the second address is expanded to full word length prior to the addition by propagating the sign bit value through the high order 16 positions The addition is completed by adding all 32 bits of both operands 2 An overflow exists if the high order numeric result bit and the carry out of ...

Страница 145: ...elation of the sum to a zero number and the occurrence of a carry out of the sign bit position An overflow on such carries is not recognized and does not set an interrupt condition I ALR IE Rl R2 0 7 8 11 12 15 I ALl 5E Rl X2 0 7 8 11 12 15 16 0 sum is zero and no carry 1 sum is not zero and no carry 2 sum is zero with a carry 3 sum is not zero with a carry Address error Addressing RX format Speci...

Страница 146: ...overflow Address error Addressing RX format Specification RX format B2 D2 19 20 31 Notes 1 The operation is accomplished by adding the one s complement of the second operand and a one in the low order position of the first operand The one s complement of a number is obtained by changing all the 1 bits to 0 bits and all the 0 bits to 1 bits All 32 bits are involved in the operation An overflow exis...

Страница 147: ... is less than zero 2 difference is greater than zero S overflow Fixed point overflow Address error Addressing Specification 31 Notes 1 The halfword in main memory specified by the second address is expanded to full word length by propagating the sign bit value through the 16 high order positions 2 The subtraction is completed by adding the one s complement of the second operand and a one in the lo...

Страница 148: ... bit position An overflow on such carries is not recognized and does not set an interrupt condition I SLR 1F R1 R2 0 7 8 11 12 15 I SL 5F R1 2 B2 0 7 8 11 12 15 16 19 0 not used 1 difference is not zero and no carry 2 difference is zero with a carry 3 difference is not zero with a carry Address error Addressing RX format SpecIfication RX format 20 31 1 Logical subtraction is accomplished by adding...

Страница 149: ...ain unaltered The result of the comparison determines the condition code setting I CR 19 Rl R2 0 7 8 11 12 15 I C 59 Rl X2 B2 D2 0 7 8 11 12 15 16 19 20 0 operands are equal 1 the operand specified by the first address is low 2 the operand specified by the first address is high 3 not used Address error Addressing RX format Specification RX format 31 Note Both operands are considered as 32 bit sign...

Страница 150: ...parison determines the condition code setting o 7 8 11 12 15 16 19 20 0 operands are equal 1 the operand specified by the first address is low 2 the operand specified by the first address is high 3 not used Address error Addressing Specification 31 Notes 1 The halfword in storage specified by the second address is expanded to full word length by propagating the sign bit value through the 16 high o...

Страница 151: ...umbered register of the pair The original contents of the even numbered register which is replaced by the product is ignored An overflow cannot occur 2 Only when two maximum negative numbers are multiplied does the product exceed 62 significant bits This product produces 63 signifi cant bits 3 In two s complement notation the sign bit is propagated right up to the first significant product bit 4 T...

Страница 152: ...iplication by propagating the sign bit value through the 16 high order positions Both operands are considered as 32 bit signed integers The multiplicand is replaced by the low order 32 bits of the product The product usually occupies 46 bits of significance except when both operands are maximum negative numbers and occupy 47 bits 2 The bits to the left of the 32 low order bits of the product are n...

Страница 153: ... error Addressing RX format Specification Divide Error Notes 1 The dividend a 64 bit signed integer is replaced by a 32 bit signed quotient and a 32 bit signed remainder the remainder is placed in the even numbered register and the quotient is placed in the odd numbered register The divisor is a 32 bit signed integer and is unaltered 2 A divide error interrupt occurs when the magnitude of the divi...

Страница 154: ... Unchanged Address error Addressing Specification Data error Divide error 1 The double word operand in main memory 15 digits plus sign must be in the packed decimal format The operand is checked for valid sign and digit codes The sign representation depends on the current decimal code USASCII or EBCDIC 2 The maximum decimal number that can be converted and still be contained in a 32 bit register i...

Страница 155: ...ified signed integer before and after the conversion o 7 8 11 12 15 16 19 20 Unchanged Address error Addressing Specification Protection 31 Notes 1 The result is placed in the double word main memory location in the packed decimal format of 15 digits plus sign 2 The low order four bits of the result are the sign which is generated according to the current decimal code EBCDIC or USASCII 3 The maxim...

Страница 156: ...rst address R1 is stored in the main memory location specified by the second address XdB2 D2 o 7 8 11 12 15 16 19 20 Unchanged Address error Addressing Specification Protection 81 1 The complete contents 32 bits of the general register specified by the first address are placed unaltered in main memory 2 The operand specified by the first address is unaltered 147 ...

Страница 157: ... by the first address R1 is stored unaltered in the halfword main memory location specified by the second address X2 B2 D2 o 7 8 11 12 15 16 19 20 Unchanged Address error Addressing Specification Protection 31 Notes 1 The 16 high order bits of the operand specified by the first address field are ignored by the operation 2 The operand specified by the first address is unaltered 148 ...

Страница 158: ...where the first operand word is to be stored Storing of the operands continues in the ascending order of the register number specified by R1 up to and including R3 storing as many words as indicated in the main memory locations that immediately follow the initial operand o 7 8 11 12 15 16 19 20 31 Unchanged Address error Addressing Specification Protection 1 If the same register is specified for R...

Страница 159: ... not to address data The low order six bits of the second address constitute the count The remaining bits are ignored 8B o 7 8 11 12 15 16 19 20 31 0 result is zero 1 result is less than zero 2 result is greater than zero 3 overflow Fixed point overflow 1 All 31 bit positions of the integer are shifted The sign is not altered Zeros are inserted in the right hand end of the operand for each shift 2...

Страница 160: ...11 12 15 16 19 20 31 0 result is zero 1 result is less than zero 2 result is greater than zero 3 not used None 1 All 31 bit positions of the integer are shifted The sign is not altered The sign bit is propagated through the positions vacated in the left end of the operand The bits shifted out to the right are lost 2 Shifting to the right is equivalent to low order truncation or division by powers ...

Страница 161: ...ess is used as a count and not to address data The low order six bits of the second address field constitute the count The remaining bits are ignored 8F o 7 8 11 12 16 16 0 result is zero 1 result is less than zero 2 result is greater than zero 3 overflow Fixed point overflow Address error Specification 19 20 31 Notes 1 All 63 bit positions of the integer are shifted The sign bit posi tion 0 in th...

Страница 162: ...address is used as a count and not to address data The low order six bits of the second address constitute the count The remaining bits are ignored 8E o 7 8 11 12 15 16 0 result is zero 1 result is less than zero 2 result is greater than zero 3 not used Address error Specification 19 20 31 1 All 63 bit positions of the integer are shifted The sign bit in the leftmost position of the even numbered ...

Страница 163: ...st byte of a field contain the sign of the field Decimal arithmetic instructions operate from right to left The addresses specify the leftmost byte of the operand and the length specifies the addi tional number of bytes that are to the right of the addressed byte The fields specified by the addresses can be variable in length beginning at any byte in main memory and consisting of from 1 to 16 eigh...

Страница 164: ...nerated Sign Zone Plus Minus 1100 1101 1111 When the decimal code bit is set for USASCII the following codes are generated Sign Zone Plus Minus 1010 1011 0101 Note The codes 1110 2 and 1111 2 are accepted as plus signs However if an arithmetic operation is performed on a field with these signs the sign of the result will be in EBCDIC or USASCII as shown above Decimal arithmetic instructions use th...

Страница 165: ...l Low High The following interrupt conditions can occur as a result of a decimal arithmetic instruction Addressing An address error interrupt exists when an address specifies a location outside the available main memory of the particular installation The operation is terminated at the point of error The result data and the condition code are unpredictable Specification An address error interrupt e...

Страница 166: ...ignoring the overflow data and setting the condition code to 3 If the decimal overflow program mask bit is reset interrupt will not occur and the flag in the IFR will not be set Divide Error A divide error interrupt occurs when the quotient is greater than the specified data field including division by zero or the dividend does not have one leading zero Division is suppressed and the dividend and ...

Страница 167: ...low Two conditions which cause overflow are 0 1 a carry out of the high order position of the result 2 a second operand that is larger than the first operand and significant result positions are lost FA I Ll I L2 I Bl I Dl 7 8 11 12 15 16 19 20 31 32 35 36 47 o sum is zero 1 sum is less than zero 2 sum is greater than zero 3 overflow Address error Addressing Protection Data error Decimal overflow ...

Страница 168: ... their rightmost byte location must coincide The subtraction of two operands can cause decimal overflow FB o 7 8 11 12 15 16 19 20 31 32 35 36 47 0 difference is zero 1 difference is less than zero 2 difference is greater than zero 3 overflow Address error Addressing Protection Data error Decimal overflow 1 High order zeros are supplied for either operand during instruction execution 2 All signs a...

Страница 169: ...rightmost byte locations coincide or if the rightmost byte of the first operand is to the right of the rightmost byte of the second operand A second operand that is longer than the first operand causes overflow F8 o 7 8 11 12 15 16 19 20 0 result is zero 1 result is less than zero 2 result is greater than zero 3 overflow Address error Addressing Protection Data error Decimal overflow 31 32 35 36 4...

Страница 170: ...equal in length the shorter is extended with high order zeros If operands overlap their rightmost byte location must be identical Overflow cannot occur as a result of this operation F9 o 7 8 11 12 15 16 19 20 31 32 35 36 47 0 the fields are numerically equal 1 the first operand is algebraically less than the second operand 2 the first operand is algebraically greater than the second operand Addres...

Страница 171: ...er than the first operand multiplicand and must not exceed eight bytes in length 15 digits plus sign Otherwise an address error specification occurs The multiplicand must have high order zero bytes equal to the number of bytes in the multiplier field or a data error occurs The maximum product size is 31 digits Fe o 7 8 11 12 15 16 19 20 Unchanged Address error Addressing Protection Specification D...

Страница 172: ...n occurs The dividend must have at least one high order zero Otherwise a data error occurs Together the quotient and remainder occupy the entire dividend field after division Therefore the address of the quotient field is the address of the dividend field and its size in bytes is Ll L2 The quotient and remainder are signed integers which are right aligned in the first operand No overflow can occur...

Страница 173: ...d All other zones are ignored The four bit numeric portions stripping the four bit zone of each byte are then placed adjacent to the sign and to each other to fill the result field The result is extended with high order zeros if the second operand field is shorter than the first If the first operand field is not large enough to contain all the significant digits from the second operand field the r...

Страница 174: ...BCDIC a zone code of 1111 is inserted into the high order four bits of each byte If the Decimal Code is USASCII a zone code of 0101 is inserted These zones are inserted in all but the zone portion of the right most byte which receives the sign of the packed operand If the first operand is not large enough to receive the significant digits of the second operand the remaining digits are ignored The ...

Страница 175: ...e enough to receive all bytes of the second operand the remaining bytes are ignored If the second operand is shorter than the first operand the second operand is extended with high order zeros The first and second operands may overlap F1 o 7 8 11 12 15 16 19 20 31 32 35 36 47 Unchanged Address error Addressing Protection 1 Signs and digits are not checked for validity 2 The second operand is not c...

Страница 176: ...volves the entire 32 bits There is no distinction made between sign and numeric bits In some operations only the least significant eight bits of the general register are involved and in another case the least significant 24 bits are involved In addition there are some shift operations in which an even odd numbered pair of general registers is involved The storage data in memory to register operati...

Страница 177: ... general registers specified by X2 and B2 are added to the contents of the D2 field R5 Format o 7 8 11 12 15 16 19 20 31 Description In the RS format which is only used for shift instructions in this instruction set the contents of the general register specified by Rl are called the first operand There is no actual storage address formed by adding the contents of the general register specified by ...

Страница 178: ...Zero OR Zero Not Zero One Test Under Mask Zero Mixed Translate and Test Zero Incomplete Complete Test and Set Zero One The following interrupt conditions can occur as a result of logical instructions An address error interrupt occurs when an address specifies a loca tion outside the available memory At the point of error the operation is terminated The result data and condition code if affected ar...

Страница 179: ...ction being executed is stored in the main memory location specified by the first address BdD1 I MVI 92 I 12 I Bl I 0 7 8 15 16 19 20 31 I MVC D2 I L I Bl I 0 7 8 15 16 19 20 31 32 35 36 47 Unchanged Address error Addressing Protection Notes 1 The bytes being moved are not inspected or changed 2 Processing is from left to right and overlapping of fields is permitted 3 The second operand is not alt...

Страница 180: ...tion operand specified by the first address B1 D1 Dl L o 7 8 15 16 19 20 31 32 35 36 47 Unchanged Address error Addressing Protection Notes 1 The numerics are not changed or checked for validity 2 The operand specified by the second address is not altered unless operands overlap 3 Processing is from left to right 4 The high order four bits of the source and destination operand bytes are not altere...

Страница 181: ...nation operand specified by the first address B1 D1 D3 L o 7 8 15 16 19 20 31 32 35 36 47 Unchanged Address error Addressing Protection Notes 1 The zones are not changed or checked for validity 2 The operand specified by the second address is not altered unless operands overlap 3 Processing is from left to right 4 The low order four bits of the source and destination operand bytes are not altered ...

Страница 182: ... is zero 1 Leftmost bit of byte specified is one Addressing Power Failure Machine check Notes 1 The leftmost bit bit position 0 of the byte located at the first operand address is used to set the condition code and the entire addressed byte is set to all ones 2 The operation is terminated on any protection violation The condi tion code setting is unpredictable when a protection violation occurs 3 ...

Страница 183: ...uality or when the operand bytes have been exhausted I CLR 15 I Rl I R2 I 0 7 8 11 12 15 CL 55 I Rl I X2 I B2 D2 0 7 8 11 12 15 16 19 20 31 I CLI 95 I 12 I Bl I Dl o 7 8 15 16 19 20 31 I CLC D5 I L I Bl I Dl B2 o 7 8 15 16 19 20 31 32 35 36 0 the operands are equal 1 the first operand is less than the second operand 2 the first operand is greater than the second operand 3 not used Address error Ad...

Страница 184: ...etermines the condition code NR 14 I Rl I R2 0 7 8 11 12 15 N 54 I Rl I X2 0 7 8 11 12 15 NI 94 12 0 7 8 15 I NC D4 I L 0 7 8 15 0 result is zero 1 result not zero 2 not used 3 not used Address error I I B2 16 19 20 I Bl I 16 19 20 I Bl I 16 19 20 Addressing RX SI SS only Protection SI SS only Specification RX only D2 31 Dl 31 Dl B2 D2 31 32 35 36 47 1 The second operand is unaltered unless operan...

Страница 185: ... the condition code OR 16 I R1 I R2 I 0 7 8 11 12 15 0 56 I R1 I X2 I B2 0 7 8 11 12 15 16 19 20 01 96 12 I B1 I 0 7 8 15 16 19 20 I oe D6 I L I B1 I 0 7 8 15 16 19 20 0 result is zero 1 result is not zero 2 not used 3 not used Address error Addressing RX SI SS only Protection SI SS only Specification RX only D2 31 D1 31 D1 B2 D2 31 32 35 36 47 Notes 1 The second operand is unaltered unless operan...

Страница 186: ...ress R1 or BdDd and determines the condition codes I XR 17 I Rl I R2 I o 7 8 11 12 15 o 7 8 11 12 15 16 19 20 XI 97 o 7 8 15 16 19 20 I XC D7 I o 7 8 15 16 19 20 0 result is zero 1 result is other than zero 2 not used 3 not used Address error Addressing RX SI SS only Protection SI SS only Specification RX only D2 31 Dl 31 Dl B2 D2 31 3235 36 47 Notes 1 The second operand is unaltered unless operan...

Страница 187: ...ght bit mask and is made to correspond one for one with the bits of the byte in main memory that is specified by the first address A bit in the byte being examined is said to be selected when the corre sponding mask bit is a one When the mask bit is a zero the bit in main memory is ignored 91 o 7 8 15 16 19 20 31 0 selected bits all zero or mask is all zero 1 selected hits mixed zero and one 2 not...

Страница 188: ...ied by the second address XdBdD2 is loaded into the rightmost byte of the general register specified by the first address R1 The remaining bits of the register are unaltered 43 I Rl I x2 I B2 I D2 0 7 8 11 12 15 16 19 20 31 Unchanged Address error Addressing The operand specified by the second address is not altered or inspected 179 ...

Страница 189: ...tmost eight bit byte of the general register specified by the first address R2 is stored into the main memory location specified by the second address XdBdD2 42 o 7 8 11 12 15 16 19 20 31 Unchanged Address error Addressing Protection Note The operand specified by the first address is not altered or inspected 180 ...

Страница 190: ...by the first address Any carry beyond the rightmost 24 bits is ignored 41 o 7 8 11 12 15 16 19 20 31 Unchanged None 1 All specified address arithmetic is computed before loading 2 Rh X2and B2 may specify the same register however Rl only may specify register o 3 This instruction can be used to increment the low order 24 bits of a general register other than 0 by the contents of the D2 field The re...

Страница 191: ...rting location of a translation table This sum in turn addresses a byte location within the table containing a function byte The function byte at this location replaces the original argument byte of the first operand The operation terminates when the first operand bytes have been exhausted DC L o 7 8 15 16 19 20 31 32 35 36 47 Unchanged Address error Addressing Protection Notes 1 The translation t...

Страница 192: ...byte is not all zeros the instruction inserts the address of the argument byte in the low order 24 bits of General Register 1 13 or 9 and inserts the retrieved non zero function byte in the low order eight bits of General Register 2 14 or 10 The high order eight bits of General Register 1 13 or 9 and high order 24 bits of General Register 2 14 or 10 are unaltered The operation terminates when a no...

Страница 193: ...s sign control punctuation control zero suppression or check protection and also facilitates blanking of all zero fields In addition mUltiple fields of digits can be edited in one operation and numeric data can be combined with alphabetic and special characters Editing rules depend on the control code significance and the source digit and are given as follows Editing Rules Control Codes Hexadecima...

Страница 194: ...8 Field separator codes 22 16 are always replaced by the filler character Note The filler character is obtained from the mask pattern as part of the editing operation The first character leftmost byte of the mask pattern is used as a filler character and is left unchanged in the result except a when it is a digit select code b when it is a start significance code In these codes a source digit is e...

Страница 195: ...ifies USASCII the zone code 0101 is generated 5 The rightmost four bits of any source field byte can be a digit or sign as follows Codes Deflnition 0000 1001 Digits 1010 1100 1110 1111 Plus sign 1011 1101 Minus sign 6 Overlapping of fields yields unpredictable results 7 In testing for Paging Error or Paging Queue interrupt conditions the hardware assumes that the number of bytes in the source fiel...

Страница 196: ...The Edit and Mark instruction facilitates the insertion of floating cur rency symbols sign indicators relational operators and other editing symbols etc The address loaded into the register is one byte to the right of the address where such a symbol would be inserted The Branch on Count instruction with zero in the R2 field can be used to reduce the loaded address by one Because the address is not...

Страница 197: ...P2 General Register 1 is used In processor state P3 General Register 13 is used In processor state P4 General Register 9 is used 6 In testing for Paging Error or Paging Queue interrupt conditions the hardware assumes that the number of bytes in the source field is equal to the number of bytes in the pattern field If the assumed source field extends across two pages of which the second page has any...

Страница 198: ...nd address B2 D2 The R3 field is ignored The second address does not refer to a main memory location The low order six bits of the second address are used as the count to specify the number of bits of shifting to be done The remaining bits are ignored 89 o 7 8 11 12 15 16 19 20 31 Unchanged None 1 High order bits of the register are shifted out and lost 2 Zeros are placed into the right end of the...

Страница 199: ...2 D2 The R3 field is ignored The second address does not refer to a main memory location The low order six bits of the second address are used as the count to specify the number of bits shifting to be done The remaining bits are ignored 88 o 7 8 11 12 15 16 19 20 31 Unchanged None 1 Low order bits of the register are shifted out and lost 2 Zeros are placed into the left end of the register 3 All 3...

Страница 200: ...nored The second address does not refer to a main memory location The low order six bits of the second address are used as the count to specify the number of bits of shifting to be done The remaining bits are ignored 0 8D I Rl I R3 I B2 I D2 7 8 11 12 15 16 19 20 31 Unchanged Address error l 2 3 4 Specification The first address must specify an even numbered register All 64 bits of the double leng...

Страница 201: ...he second address does not refer to a main memory location The low order six bits of the second address are used as the count to specify the number of bits of shifting to be done The remaining bits are ignored 8e I Rl I R3 I B2 I D2 0 7 8 11 12 15 16 19 20 31 Unchanged Address error Specification Notes 1 The first address must specify an even numbered register 2 All 64 bits of the double length op...

Страница 202: ...n is entailed by use of this instruction The branch address in this instruction specifies one instruction to be executed in the instruction sequence The address in the P counter is not replaced by the branch address and only the instruction located at the address is executed before the sequence is continued based upon the updated P counter Normally the P counter instruction address specifies a mai...

Страница 203: ...struction the M field is a mask that specifies the condition codes to be tested Notes 1 A zero in the X2or B2 field indicates that the corresponding address component is absent 2 The sequence of operations when using general registers is as follows a compute the address b store arithmetic or link information c replace the P counter with the branch address Interrupts can occur as a result of an Exe...

Страница 204: ...a corresponding mask bit set 0 0 BCR 07 Ml R2 7 8 11 12 15 BC 47 M X2 B2 D2 7 8 11 12 15 16 19 20 31 Unchanged None 1 The four bit mask in Ml corresponds left to right with the four condition codes Instruction Bit Condition Code 8 0 9 1 10 2 11 3 2 If all mask bits are set M1 F1G an unconditional branch is effected 3 When all mask bits are zero or if R2 in the RR format is zero the instruction is ...

Страница 205: ...on address is replaced BALR 05 RI R2 0 7 8 11 12 15 BAL 45 RI X2 B2 D2 0 7 8 11 12 15 16 19 20 31 Unchanged None 1 The P counter is stored without branching in the RR format when the R2 field is zero 2 When a branch occurs the leftmost eight bit portion of the 32 bit P counter ILC CC and mask is unpredictable However the actual condition code and program mask hardware registers are unaffected by b...

Страница 206: ...l count of zero in the Rl field results in branching because subtraction occurs before testing the contents of the register If the value is zero branching occurs and the result is minus one To effect a no branch the contents of the Rl field must be 1 3 The contents of the registers specified by the second address are unaltered 4 When branching occurs the leftmost eight bit portion of the 32 bit P ...

Страница 207: ...ccur and the next instruction is executed If the sum is high the instruction address in the P counter is replaced by the branch address B2 D2 and branching occurs o 7 8 11 12 15 16 19 20 31 Unchangtd None 1 The sum replaces the operand specified by the first address R1 regardless of the comparison The sum replaces R1 after the comparison has been made 2 Overflow is not recognized 3 The contents of...

Страница 208: ...he next instruction in sequence is executed If the sum is low or equal the instruction address in the P counter is replaced by the branch address B2 D2 and branching occurs o 7 8 11 12 15 16 19 20 31 Unchanged None 1 The sum replaces the operand specified by the first address R1 regardless of the comparison The sum replaces R1 after the comparison has been made 2 Overflow is not recognized 3 The c...

Страница 209: ...fied and executed Address error Addressing Specification Notes 1 Bits 8 15 of the subject instruction are OR ed with bits 24 31 of the register specified by the first address R1 2 If Rl is zero no modification takes place 3 The ILC is set to two length of the Execute and the P counter is set to the address of the instruction following the Execute instruction 4 The contents of Rl and the subject in...

Страница 210: ...on subtraction mUltiplication and division produce normalized results Addition and subtraction can also produce unnormalized results Operands can be normalized or unnormalized in any floating point operation Sign control add subtract and compare operation results are indicated in the condition code settings Floating point numbers are fixed in length and are either full word short or double word lo...

Страница 211: ...ed number into a normalized number the man tissa is shifted to the left until the high order digit is non zero Then the exponent is decremented by the number of digits shifted Generally normalization occurs when the intermediate arithmetic result is changed to the final result However in multiplication and division operations normalization occurs before the arithmetic process Floating point operat...

Страница 212: ...e the same general register to specify both operand locations and address generation Addresses are generated before execution The condition code reflects results of floating point sign control add subtract and compare instructions The code is not changed by any other floating point operation Decision making by branch on condition instruc tions can be done after those instructions that set the code...

Страница 213: ...y protect feature is installed Signiflcance Error A significance error interrupt occurs when the result mantissa of an add or subtract operation is zero A program interrupt occurs if the significance error mask bit in the Interrupt Mask Register of the current state is set to 1 The operation is completed the exponent is unaltered and the interrupt is taken If the significance error mask bit is zer...

Страница 214: ... Rl X2 B2 D2 0 7 8 11 12 15 16 19 20 31 RR Long LDR 28 Rl 0 7 8 11 12 15 RX Long LD 68 Rl X2 B2 D2 0 7 8 11 12 15 16 19 20 31 Condition Code Unchanged Interrupt Action Address error Addressing RX format Specification Notes 1 The operand specified by the second address is unaltered 2 Exponent overflow underflow or lost significance cannot occur 3 The low order half of the register specified by the ...

Страница 215: ...ign and magnitude of the loaded operand determine the condition code LTER 32 R1 R2 o 7 8 11 12 15 o 7 8 11 12 15 0 result mantissa is zero 1 result mantissa is less than zero 2 result mantissa is greater than zero 3 not used Address error Specification 1 If R1 and R2 are equal the operation is equivalent to a test without data movement 2 The operand specified by the second address is unaltered 3 S...

Страница 216: ...y the first address R1 and the sign is changed to the opposite value The sign and magnitude of the loaded operand determine the condition code LCER 33 o 7 8 11 12 15 LCDR 23 o 7 8 11 12 15 0 result mantissa is zero 1 result mantissa is less than zero 2 result mantissa is greater than zero 3 not used Address error Specification 1 The exponent and mantissa are unaltered 2 Short operands do not alter...

Страница 217: ...ded into the floating point register specified by the first address R1 and the operand sign is made plus 0 0 LPER 30 Rl R2 7 8 11 12 15 LPDR 20 Rl R2 7 8 11 12 15 o result mantissa is zero I not used 2 result mantissa is greater than zero 3 not used Address error Specification 1 The exponent and mantissa are unaltered 2 Short operands do not alter the low order half of the register specified by th...

Страница 218: ...2 is loaded into the floating point register specified by the first address R1 and the operand sign is made minus LNER 31 o 7 8 11 12 15 LNDR 21 o 7 8 11 12 15 0 result mantissa is zero 1 result mantissa is less than zero 2 not used 3 not used Address error Specification 1 The exponent and mantissa are unaltered 2 Short operands do not alter the low order half of the register specified by the firs...

Страница 219: ...cation Significance error Exponent overflow Exponent underflow Notes 1 To perform normalized addition the computer must scale the two operands Scaling consists of comparing the exponents of the two operands If they do not agree the mantissa with the smaller exponent operand is shifted right Its exponent is increased by one for each digit right shifted until the two exponents agree Then the mantiss...

Страница 220: ...sa length If the exponent underflows exceeds 64 during normalization the float ing point number is made true zero and an exponent underflow interrupt occurs 3 No normalization is performed when the intermediate sum is zero The sum mantissa is unaltered and a significance error interrupt occurs If a significance error interrupt is prohibited by the interrupt mask the quantity is made true zero and ...

Страница 221: ...pecified by the first address The sign and magnitude of the loaded sum determine the condition code o 7 8 11 12 15 o 7 8 11 12 15 16 19 20 o 7 8 11 12 15 o 7 8 11 12 15 16 19 20 0 result mantissa is zero 1 result mantissa is less than zero 2 result mantissa is greater than zero 3 result exponent overflows Address error Addressing RX format Specification Exponent overflow Significance 31 31 Notes 1...

Страница 222: ...dress The sign and magnitude of the difference determine the condition code o 7 8 11 12 15 o 7 8 11 12 15 16 19 20 o 7 8 11 12 15 o 7 8 11 12 15 16 19 20 0 result mantissa is zero 1 result mantissa is less than zero 2 result mantissa is greater than zero 3 result exponent overflows Address error Addressing RX format Specification Significance error Exponent overflow Exponent underflow 31 31 Notes ...

Страница 223: ...fied by the first address The sign and magnitude of the difference determine the condition code o 7 8 11 12 15 o 7 8 11 12 15 16 19 20 o 7 8 11 12 15 o 7 8 11 12 15 16 19 20 0 result mantissa is zero 1 result mantissa is less than zero 2 result mantissa is greater than zero 3 result exponent overflows Address error Addressing RX format Specification Significance error Exponent overflow 31 31 1 Sub...

Страница 224: ...l 1 operand specified by the first address is less than the one specified by the second address 2 operand specified by the first address is greater than the one specified by the second address 3 not used Address error Addressing RX f ormat Specification 1 Comparison takes into account the sign exponent and mantissa of each number Exponent inequality is not decisive for magnitude determination sinc...

Страница 225: ...oint register specified by the first address R1 HER 34 Rl 0 7 8 11 12 16 HDR 24 Rl R2 0 7 8 11 12 16 Unchanged Address error Specification Notes 1 The difference between the Halve instruction and a Divide instruction with a divisor of two is that no normalization and no zero mantissa testing takes place The sign and exponent are unaltered and the mantissa is shifted right one bit 2 Short operands ...

Страница 226: ...t address R1 are stored in the main memory location specified by the second address X2 B2 D2 STE 70 Rl X2 B2 D2 0 7 8 11 12 15 16 19 20 31 STD 60 Rl X2 B2 D2 0 7 8 11 12 15 16 19 20 31 Unchanged Address error Addressing Specification Protection Notes 1 The first operand is unaltered 2 Short operands do not alter the low order half of the register specified by the second address 217 ...

Страница 227: ...sum is reduced by 64 to form an intermediate exponent The mantissas are normal ized as described in the Add Normalize instruction and multiplied to form an intermediate mantissa The intermediate mantissa is then normalized reducing its exponent by one for each digit left shifted to form the final product 2 The sign of the product is determined by the rules of algebra 3 If the product mantissa is z...

Страница 228: ...low Divide error 1 The exponents of the two operands are subtracted and the difference is increased by 64 to form an intermediate exponent The mantissas are normalized as described in the Subtract Normalize instruction and divided to form the mantissa of the intermediate quotient The intermediate exponent and mantissa are normalized to form a final quotient 2 If the dividend first operand is zero ...

Страница 229: ...g a channel to memory data transfer the data transfer is terminated and a channel termination interrupt occurs The protected memory is unaltered and the indication of mismatch is stored in the input output channel registers in scratch pad memory for the specified channel The storage key can be changed by the privileged instruction Set Storage Key and can be inspected by the privileged instruction ...

Страница 230: ...rams of from one to five other processors over an interface independent of the input output channels The processors directly connected by this feature may be remotely located up to 500 cable feet from the transmitting processor Two additional privileged instructions are provided with this option Write Direct and Read Direct which initiate the transfer of one byte of control information between pro...

Страница 231: ......

Страница 232: ...APPENDICES 223 ...

Страница 233: ... memory Burst 5 52 CRT 2 Termination accepted Selector 6 00 CRT 3 Inoperable Idle 80 IDL SI 1 Privileged operation Unchanged 6 00 Insert Storage Key 09 ISK RR 1 Privileged operation 2 Operation code trap Unchanged 5 28 if feature not installed 3 Address error Load Scratch Pad D8 LSP SS 1 Privileged operation Unchanged 10 56 2 88R 2 Address error Program Control 82 PC SI 1 Privileged operation CC o...

Страница 234: ...ed 3 Address error Function Call 9A FC SI 1 Privileged operation 2 Operation code trap 3 Power failure 4 Machine check Unchanged To be supplied 5 Addressing 6 Paging error 7 Paging queue 8 Others as defined Special Functions Load Translation CO LTM SF 1 Addressing Memory 2 Power Failure 3 Machine Check 4 Paging Error 5 Paging Queue Scan Translation C1 STMS SF 1 Addressing Memory and 8tore 2 Power ...

Страница 235: ...re 3 Machine Check 4 Paging Error 5 Paging Queue Store Interval 03 SIT SF 1 Addressing Unchanged 9 60 Timer 2 Power Failure 3 Machine Check 4 Paging Error 5 Paging Queue Paging Queue and SF 1 Power Failure Unchanged 26 RR Instruction or 1st Paging Error 01 2 Machine Check Instruction Address Interrupt Error Service 48 2nd Instruction Address Error 110 Load Multiple Store Multiple no Instruction Ad...

Страница 236: ...ddress error 1 Surn is less than zero Add Word 2 Sum is greater than zero IA AR RR 3 Overflow 5 28 Com are Halfword 49 CH RX 1 Address error o Operands equal 1 First operand low 7 44 2 First operand high 3 Not us ed 59 C RX 1 Address error o Operands equal 8 40 Compare Word 1 First operand low 2 First operand high 19 CR RR 3 Not used 4 80 Convert to Binary 4F CVB RX 1 Address error Unchanged 2 Dat...

Страница 237: ... is zero 1 Result is less than zero 5 28 2 Result is greater than zero 3 Not used 58 L RX 1 Address error 8 88 Load Word Unchanged 18 LR RR 2 88 Multiply Halfword 4C MH RX 1 Address error Unchanged 35 40 5C M RX 1 Address error 65 64 Multiply Word 1C MR RR Unchanged 62 52 Shift Left Double 8F SLDA RS 1 Fixed Point overflow o Result is zero Under 16 11 04 0 96 N 2 Address error 1 Result is less tha...

Страница 238: ... less than zero 7 92 2 Diff greater than zero 3 Overflow 5F SL RX 1 Address error 0 Not used 8 40 Subtract Logical 1 Diff not zero no carry 2 Diff zero with carry IF SLR RR 3 Diff not zero with carry 4 80 5B S RX 1 Fixed Point overflow 0 Diff is zero 8 88 2 Address error 1 Diff less than zero Subtract Word 2 Diff greater than zero IB SR RR 3 Overflow 5 28 Decimal Arithmetic Instructions Add Decima...

Страница 239: ...or 2 34L2 Ll L2 Pack F2 PACK SS 1 Address error Unchanged 9 36 1 92L1 0 96L2 Subtract Decimal FB SP SS 1 Address error 0 Diff is zero 15 84 1 80L1 0 42L2 2 Data error 1 Diff is less than zero Note 1 3 Decimal overflow 2 Diff is greater than zero 3 Overflow Unpack F3 UNPK SS 1 Address error Unchanged 10 38 0 96L1 0 90L2 Zero and Add F8 ZAP SS 1 Address error 0 Result is zero 15 96 1 08L1 0 42L2 2 D...

Страница 240: ...d to indicate less than zero 2 Non zero result field with no signif established to indicate greater than zero 3 Not used 57 X RX 1 Address error o Result is zero 1 Result is not zero D7 XC SS 2 Not used Exclusive Or 3 Not used 97 XI SI 17 XR RR Insert Character 43 IC RX 1 Address error Unchanged Load Address 41 LA RX None Unchanged Lege l Ul B total number of bytes processed This condition occurs ...

Страница 241: ...96 16 OR RR 5 28 Shift Left Single 89 SLL RS None Unchanged Under 16 7 92 0 48 N Logical 16 to 31 11 04 0 48 N 16 32 to 47 14 16 0 48 N 32 48 to 63 17 28 0 48 N 48 Shift Right Si ngle 88 S RL RS None Unchanged Under 16 8 88 0 48 N Logical 16 to 31 11 04 0 48 N 16 32 to 47 13 20 0 48 N 32 48 to 63 13 20 0 48 N 48 Shift Left Double 8D SLDL RS 1 Address Error Unchanged Under 16 7 68 0 96 N Logical 16...

Страница 242: ...failure 1 Leftmost bit of byte specified is one Branching Instructions 45 BAL RX None Branch and Link Unchanged 05 BALR RR 47 BIC RX None Branch on Condition Unchanged 07 BCR RR 46 BCT RX None Branch on Count Unchanged 06 BGTR RR Branch on 86 BXH RS None Unchanged Index High Legend B total number of bytes processed This condition occurs if instruction terminates before L count is exhausted 6 48 9 ...

Страница 243: ...low 2 Result mantissa greater Add Normalized 7A AE RX than zero 19 20 Short 3A AER RR 3 Result exponent overflow 16 08 Add Unnormalized 6E AW RX 1 Address error o Result mantissa zero 26 81 Long 2 Significance error 1 Result mantissa less th n 2E AWR RR 3 Exponent overflow zero 21 77 7E AU RX 2 Result mantissa greater 18 96 Add Unnormalized than zero Short 3E AUR RR 3 Result exponent overflow 15 8...

Страница 244: ...gative 31 LNER RR 2 Not used 5 52 Short 3 Not used Load Positive 20 LPDR RR 1 Address error o Result mantissa zero 7 68 Long 1 Not used 2 Result mantissa greater Load Positive 30 LPER RR than zero 5 52 Short 3 Not used Load and Test 22 LTDR RR 1 Address error o Result mantissa zero Long 1 Result mantissa less than 8 16 zero Load and Test 32 LTER RR 2 Result mantissa greater Short than zero 6 00 3 ...

Страница 245: ...ero 3 Result exponent overflow 19 20 SER RR 16 08 SW RX 1 Address error o Result mantissa zero 26 81 2 Significance error 1 Result mantissa less than 3 Exponent overflow zero SWR RR 2 Result mantissa greater 21 77 than zero SU RX 3 Result exponent overflow 18 96 SUR RR 15 84 Notes 1 Time for Ll L2 and no End Around Carry Additional time must be added if L2 Ll or End Around Carry 2 If the two field...

Страница 246: ...pro cessor or memory 11 64 Parity error or equip fl 64 ment malfunction 11 64 Signal received on 11 64 one of the six ex 11 64 ternal lines asso ciated with the di 11 64 rect control feature 11 64 11 64 Lapse of Interval Timer 14 64 18 86 CRT 18 86 CRT A device on the asso ciated selector or 18 86 CRT multiplexor channel has terminated 25 90 CRT Elapsed time count has expired 13 08 Manual request ...

Страница 247: ...ic of floating point oper 13 08 ation is greater than 127 Rules pertaining to Divide instruction have 13 08 been violated Result of floating point or subtract has zero 13 08 fraction Result characteristic of floating point oper 13 08 ation is less than zero Result field is too small to contain the result of 13 08 a decimal operation High order carry or high order significant 13 08 bits lost in fix...

Страница 248: ... 13 44 3 Command Chaining Mux Mode 12 96 b 4 Command Chaining Burst Mode 6 72 b 5 Transfer in Channel 4 32 6 Status Modifier 1 92 7 Catch up each additional byte 1 92 E Processing Mode Times 1 START I O addr the selector 32 64 b 2 START I O addr the multiplexor 39 6 b 3 Multiplexor Program Interrupt 25 90 b 4 Selector Program Interrupt 18 86 b NOTES a Because of odd even ROM addressing banking may...

Страница 249: ... 1111 0 1 2 3 4 5 Bit Positions 0 1 2 3 4 5 6 7 Significance 27 26 25 24 23 22 21 20 Control Characters NUL PF HT LC DEL RES NL BS IL All Zero Bits Punch Off Horizontal Tab Lower Case Delete Restore New Line Backspace Idle 6 7 8 9 A 8 0110 0111 1000 1001 1010 1011 LC DEL BS EOB UC f 0 w F 0 W 6 240 IL PRE EOT g p x G P X 7 h q y H Q Y BYP LF EOB PRE SM PN RS UC EOT 8 SM 1 A i r z I R Z 9 Bypass Li...

Страница 250: ...CR SO SI DLE DCI DC2 punch card skip FE Line Feed FE Vertical Tabulation FE Form Feed FE Carriage Return FE Shift Out Shift In Data Link Escape CC Device Control I Device Control 2 5 6 0101 0110 ENQ ACK NAK SYN 5 6 E F U V e f u v 241 7 0111 BEL ETB 7 G W g w 8 9 A B C D 1000 1001 1010 1011 1100 1101 BS HT LF VT FF CR CAN EM SUB ESC FS GS 8 9 H I J K L M x Y Z h i j k I m x y z I DC3 Device Contro...

Страница 251: ... 9 8 2 0000 1011 12 9 8 3 0000 1100 12 9 8 4 0000 1101 12 9 8 5 0000 1110 12 9 8 6 0000 1111 12 9 8 7 0001 0000 12 11 9 8 1 0001 0001 11 9 1 0001 0010 11 9 2 0001 0011 11 9 3 0001 0100 11 9 4 0001 0101 11 9 5 0001 0110 11 9 6 0001 0111 11 9 7 0001 1000 11 9 8 0001 1001 11 9 8 1 0001 1010 11 9 8 2 0001 1011 11 9 8 3 0001 1100 11 9 8 4 0001 1101 11 9 8 5 0001 1110 11 9 8 6 0001 1111 11 9 8 7 0010 00...

Страница 252: ...8 6 plus 79 4F 0100 1111 12 8 7 I vertical 80 50 0101 0000 12 ampersand 81 51 0101 0001 12 11 9 1 82 52 0101 0010 12 11 9 2 83 53 0101 0011 12 11 9 3 84 54 0101 0100 12 11 9 4 85 55 0101 0101 12 11 9 5 86 56 01010110 12 11 9 6 87 57 0101 0111 12 11 9 7 88 58 0101 1000 12 11 9 8 89 59 0101 1001 11 8 1 90 L 0101 1010 11 8 2 exclamation 91 5B 0101 1011 11 8 3 dollar sign 92 5C 0101 1100 11 8 4 asteri...

Страница 253: ...0 82 1000 0010 12 0 2 131 83 1000 0011 12 0 3 132 84 1000 0100 12 0 4 133 85 1000 0101 12 0 5 134 86 1000 0110 12 0 6 135 87 1000 0111 12 0 7 136 88 1000 1000 12 0 8 137 89 1000 1001 12 0 9 138 8A 1000 1010 12 0 8 2 139 8B 1000 1011 12 0 8 3 140 8C 1000 1100 12 0 8 4 141 8D 1000 1101 12 0 8 5 142 8E 1000 1110 12 0 8 6 143 8F 1000 1111 12 0 8 7 144 90 1001 0000 12 11 8 1 145 91 1001 0001 12 11 1 14...

Страница 254: ...9 394 531 25 0 000 003 814 697 265 625 0 000 001 907 348 632 812 5 0 000 000 953 674 316 406 25 0 000 000 476 837 158 203 125 0 000 000 238 418 579 101 562 5 0 000 000 119 209 289 550 781 25 0 000 000 059 604 644 775 390 625 0 000 000 029 802 322 387 695 312 5 0 000 000 014 901 161 193 847 656 25 0 000 000 007 450 580 596 923 828 125 0 000 000 003 725 290 298 461 914 062 5 0 000 000 001 862 645 14...

Страница 255: ... significant hexadecimal digit 16 Example c Z 310510 HEX 0 1 i CO 3072 3073 3074 C1 3088 3089 3090 C2 3104 3106 C3 3120 31 1 3122 For numbers outside the range of the table add the following values to the table figures Hexadecimal Decimal Hexadecimal Decimal 1000 4 096 COOO 49 152 2000 8 192 DOOO 53 248 3000 12 288 EOOO 57 344 4000 16 384 FOOO 61 440 5000 20 480 10000 65 536 6000 24 576 20000 131 ...

Страница 256: ...487 0488 0489 0490 0491 0492 0493 0494 0495 1F 0496 0497 0498 0499 0500 0501 0502 0503 0504 0505 0506 0507 0508 0509 0510 0511 a 1 2 3 4 5 6 7 8 9 A B C D E F 20 0512 0513 0514 0515 0516 0517 0518 0519 0520 0521 0522 0523 0524 0525 0526 0527 21 0528 0529 0530 0531 0532 0533 0534 0535 0536 0537 0538 0539 0540 0541 0542 0543 22 0544 0545 0546 0547 0548 0549 0550 0551 0552 0553 0554 0555 0556 0557 05...

Страница 257: ...0 1511 1512 1513 1514 1515 1516 1517 1518 1519 5F 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 0 1 2 3 4 5 6 7 8 9 A B C D E F 60 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 61 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 62 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581...

Страница 258: ...535 2536 2537 2538 2539 2540 2541 2542 2543 9F 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 0 1 2 3 4 5 6 7 8 9 A B e 0 E F AO 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 Al 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 A2 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 26...

Страница 259: ...58 3559 3560 3561 3562 3563 3564 3565 3566 3567 DF 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 0 1 2 3 4 5 6 7 8 9 A B C D E F EO 3584 3585 3586 3587 3588 3589 3590 359l 3592 3593 3594 3595 3596 3597 3598 3599 El 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 E2 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 362...

Страница 260: ...L GENERAL GEN ER AL GENERAL GENERAL PURPOSE PURPOSE PUR POSE PURPOSE PURPOSE PURPOSE PURPOSE PURPOSE PURPOSE PURPOSE PURPOSE PUR POSE PURPOSE PURPOSE REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER 1 10 0 NO 1 NO 2 NO 3 NO 4 NO 5 NO 6 NO 7 NO 8 NO 9 1 10 10 1 10 11 1 10 12 1 10 11 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P...

Результаты поиска

Содержание 70/46

Отзывы:

Бренды по названию

Популярные бренды

RCA 70/46, Справочное руководство

Результаты поиска

Содержание 70/46

Отзывы:

Бренды по названию

Популярные бренды