RAYLAN TLX7500, Схематические диаграммы, Страница: 3 / 10

1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
A_DDR3_CLK#
A_DDR3_VREF A_DRAM_DDR3_VREF
A_DDR3_ODT
A_DDR3_VREF
A_DDR3_CLK
A_DDR3_MA3
A_DDR3_MBA0
A_DDR3_MRAS_B
A_DDR3_MCAS_B
A_DDR3_MA10
A_DDR3_MA2
A_DDR3_MA9
A_DDR3_MA4
A_DDR3_MA5
A_DDR3_MA6
A_DDR3_MA12
A_DDR3_MA0
A_DDR3_MA8
A_DDR3_MA11
A_DDR3_MA7
A_DDR3_MA3
A_DDR3_MA1
A_DDR3_MD3
A_DDR3_MD11
A_DDR3_MD7
A_DDR3_MD15
A_DDR3_MD9
A_DDR3_MD0
A_DDR3_MD6
A_DDR3_MD8
A_DDR3_MD1
A_DDR3_MD4
A_DDR3_MD12
A_DDR3_MD5
A_DDR3_MD14
A_DDR3_MD13
A_DDR3_MD10
A_DDR3_MD2
A_DDR3_MA9 A_DDR3_rMA9
A_DDR3_rMA7
A_DDR3_MRESET_B
A_DDR3_MA7
A_DDR3_MA0 A_DDR3_rMA0
A_DDR3_MA5 A_DDR3_rMA5
A_DDR3_MA1
A_DDR3_rMA11 A_DDR3_MA11
A_DDR3_rMA8
A_DDR3_rMA6
A_DDR3_MA8
A_DDR3_rMA1
A_DDR3_MA6
A_DDR3_rMA2
A_DDR3_rBA2
A_DDR3_MA2
A_DDR3_MBA2
A_DDR3_rWE
A_DDR3_rODT
A_DDR3_rCAS
A_DDR3_rRAS
A_DDR3_rMA3
A_DDR3_rBA0
rRESET#
A_DDR3_MWE_B
A_DDR3_MA4 A_DDR3_rMA4
A_DDR3_MBA1
A_DDR3_MA12 A_DDR3_rMA12
A_DDR3_rBA1
A_DDR3_CKE A_DDR3_rCKE
A_DDR3_rMA10
A_DDR3_MA10
A_DDR3_MD13
A_DDR3_MD8
A_DDR3_MD10
A_DDR3_MD11
A_DDR3_MD9
A_DDR3_MD14
A_DDR3_MD12
A_DDR3_MD5
A_DDR3_MD2
A_DDR3_MD7
A_DDR3_MD0
A_DDR3_MD3
A_DDR3_MD1
A_DDR3_MD4
A_DDR3_MD6
A_DDR3_rWE
A_DDR3_rCAS
A_DDR3_rRAS
A_DDR3_CLK#
A_DDR3_rMA7
A_DDR3_rMA5
A_DDR3_rMA0
A_DDR3_rMA3
A_DDR3_CLK
A_DDR3_rODT
A_DDR3_rBA0
A_DDR3_rBA1
A_DDR3_rBA2
A_DRAM_MZQ
A_DDR3_rCKE
A_DRAM_DDR3_VREF
A_DDR3_rMA1
A_DDR3_rMA2
A_DDR3_rMA4
A_DDR3_rMA6
A_DDR3_rMA12
A_DDR3_rMA10
A_DDR3_rMA9
A_DDR3_rMA11
A_DDR3_rMA8
A_DDR3_MD15
A_DDR3_DQSL
A_DDR3_DQSH#
A_DDR3_DQSL#
A_DDR3_DQSH
A_DDR3_DQMH
rRESET#
A_DDR3_rMA13
A_DDR3_MA13 A_DDR3_rMA13
A_DDR3_MA13
A_DDR3_DQML
RD15 68R
DDRIII 2G
BGA96
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
V
D
D
K
2
V
S
S
Q
E
8
V
S
S
Q
F
9
V
S
S
Q
G
1
V
S
S
Q
G
9
V
D
D
G
7
V
D
D
Q
E
9
V
D
D
Q
F
1
V
D
D
Q
H
9
V
D
D
Q
H
2
UDM
D3
UDQS
C7
UDQS#
B7
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12
N7
VREFDQ
H1
V
D
D
B
2
V
D
D
N
1
V
D
D
D
9
V
S
S
A
9
V
S
S
B
3
V
S
S
E
1
V
S
S
G
8
V
S
S
J8
CAS#
K3
RAS#
J3
WE#
L3
BA0
M2
BA1
N8
CS#
L2
CK
J7
CK#
K7
N
C
1
J1
N
C
2
J9
ODT
K1
CKE
K9
BA2
M3
V
D
D
K
8
V
S
S
J2
V
D
D
Q
D
2
V
D
D
Q
C
9
V
D
D
Q
C
1
V
D
D
Q
A
8
V
D
D
Q
A
1
V
S
S
Q
D
1
V
S
S
Q
D
8
V
S
S
Q
B
1
V
S
S
Q
B
9
N
C
3
L
1
N
C
4
L
9
N
C
5
M
7
V
S
S
Q
E
2
LDM
E7
LDQS
F3
LDQS#
G3
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
ZQ
L8
V
S
S
M
1
VREFCA
M8
V
S
S
M
9
V
D
D
N
9
V
S
S
P
1
V
S
S
T
1
V
D
D
R
9
RESET#
T2
N
C
6
T
7
A13
T3
V
S
S
T
9
V
S
S
P
9
V
D
D
R
1
U9
CD7
0.1uF
RD25
100R_1%
RD23 68R
RD21 68R
RD18 68R
CD6
0.1uF
RD30
2K_1%
RD3 68R
CD1
10pF
CD8
0.1uF
RD2 68R
RD9 68R
RD26
100R_1%
RD29
2K_1%
RD14 68R
RD13 68R
CD2
NC/100nF
CD9
0.1uF
RD5 68R
CD14
0.1uF
CD3
NC/100nF
RD27
2K_1%
RD19 68R
RD20
240R_1%
RD7 68R
CD11
0.1uF
CD5
0.1uF
RD6 68R
RD28
2K_1%
RD17 68R
CD4
0.1uF
CD10
0.1uF
RD22 68R
RD10 68R
RD12 68R
RD4 68R
CD12
0.1uF
RD11 68R
RD8 68R
RD1 68R
CD13
0.1uF
RD16 68R
RD24 68R
DDR_VDD15 DDR_VDD15
DDR_VDD15
GND
GND
GND GND
DDR_VDD15
GND
GND
DDR_VDD15
GND
GND
The trace of DDR VREF should as wide as possible, suggest 20mils,
and the de-coupling cap. should be close to VREF pin.
Power bypass cap. for DDR3 Device
Power bypass cap. for VREF
There are two 100nF and one 10uF bypass for each
DDR device 1.5V power.
max:2Gb
A_DDR3_DQML
A_DDR3_DQMH
A_DDR3_DQSL#
A_DDR3_DQSL
A_DDR3_DQSH
A_DDR3_DQSH#
A_DDR3_MWE_B
A_DDR3_MCAS_B
A_DDR3_MRAS_B
A_DDR3_CLK
A_DDR3_CLK#
A_DDR3_ODT
A_DDR3_MRESET_B
A_DDR3_MBA1
A_DDR3_MBA0
A_DDR3_MBA2
A_DDR3_CKE
A_DDR3_ODT
A_DDR3_MWE_B
A_DDR3_MCAS_B
A_DDR3_MRAS_B
A_DDR3_DQSH
A_DDR3_DQSH#
A_DDR3_DQSL
A_DDR3_DQSL#
A_DDR3_DQMH
A_DDR3_DQML
A_DDR3_CLK
A_DDR3_CLK#
A_DDR3_CKE
A_DDR3_MRESET_B
A_DDR3_MBA0
A_DDR3_MBA1
A_DDR3_MBA2
ClassName: DDR3_CTRL
A_DDR3_MA[0..13]
A_DDR3_MA[0..13]
A_DDR3_MD[0..15]
A_DDR3_MD[0..15]
A_DDR3_VREF