Ramsey Electronics FM100B, Инструкция по эксплуатации

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FM100B
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that all this data transfer would take a long time. The fact is that the whole
process from the time you press a frequency control switch until the data is
completely sent is less than 1/100th of a second!
So how does this PLL and VCO (Voltage Controlled Oscillator) work in our
FM100B? While there are not a lot of parts surrounding U2, there is a lot going
on inside behind the scenes. In order for you to understand what goes on
behind the scenes, a little PLL theory wouldn’t hurt.
Let’s say for example we want to generate 100.9 MHz. Our microcontroller will
send a digital code to U2 equivalent to 1009 plus some configuration bits. This
number is moved into a divider inside of U2 were it divides down our current
operating frequency. The operating frequency is what our Voltage Controlled
Oscillator circuit consisting of C7, L1, C8, D1 and an oscillator inside of U2 are
running at. There are some more parts in our oscillator that come into play, but
we will only consider these for now (the rest are for modulating the signal with
audio and our multiplex information). This VCO frequency is sampled and then
divided by the divider value of 1009. It is then compared to a reference
frequency generated by X2 (7.6 MHz) divided by 76 which is 100 kHz.
If the desired frequency is less than the reference frequency, U2 sends
negative going pulses out of pin 7. This in turn increases the voltage on the
collector of Q4 (we will get back to this) causing an increase in the voltage
across diode D1 (the main varactor diode in our oscillator circuit). As the
voltage across the varactor increases, it causes a decrease in capacitance
(Increasing reverse bias essentially increases the distance between the
capacitor’s plates by increasing the depletion region in the diode (C = kA/d).
The decrease in capacitance causes an increase in U2’s RF oscillator (f
o
= 1/[2
π
(LC)
½
]), bringing the FM100B’s output frequency back on frequency. If the
desired frequency is higher than the reference, pin 7 has positive going pulses
and the collector voltage of Q4 is driven lower. If the frequency is just right then
pin 7 idles (basically disconnecting itself from the circuit) so it will cause no
change in the voltage on D1. The voltage changes on pin 7 are filtered by R21,
C23, R26, C28, R22, Q3, and Q4 to provide a steady, noise free tuning voltage
for D1. The group of components around Q3 and Q4 is called an Integrator.
They sum together those positive and negative going pulses from pin 7. In this
way the output frequency of U2 is "locked" to that desired by the
microcontroller.
While the PLL is constantly adjusting itself to stay on the desired frequency, U1
is polling the voltage present on the collector of Q4 to determine whether or not
the PLL is locked. The voltage is sampled at the junction of the voltage divider
R37 and R40. This divider will take the +12V range that is used in the PLL
circuit and convert it to a +5V range. U1 cannot handle voltages over 5V so this
division makes it compatible. U1 (through digital math) then converts the
numbers back to 0-12V on the display. To determine if the loop is locked, U1
performs some math to see if the tuning voltage matches the current requested