Rx-URME-031 Rev -
- DRAFT -
PMC551 Hardware Reference and Installation Manual
Page 7
4
PMC551 Architecture
The PMC551 is a complete I/O subsystem, illustrated in the block diagram.
4.1
PMC551 Subsystems
The PMC551 features an integrated PCI interface with SDRAM (Synchronous DRAM) memory
controller.
4.1.1
Memory Store
Memory configurations range from 32Mbyte to 1Gbyte. All internal configuration information is set
during manufacture by RAMiX. A feature of the memory technology used on the PMC551
(SDRAM) requires that the memory be brought to an operational state. This requires performing a
sequence of PCI configuration transfers (see the
Programming Notes
section for details).
4.1.2
PCI Interface
The PCI interface on the PMC551 is fully compliant with the PCI 2.1 specification. For data
transfer (i.e., access to the memory system), it responds to all PCI READ and WRITE
transactions. Configuration and setup is performed using PCI Configuration cycles.
The available memory on a PMC551 can be determined using the standard PCI procedure to
query a device for required address space (see the
Programming Notes
section).
Note: (the requested address range will correspond to the amount of memory actually configured on the
card, not the maximum possible.)
Host PCI
PCI Interface
PMC Connection to
Host
SDRAM Controller
Memory
Store