Radyne DM240XR, Инструкция по установке и эксплуатации

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DM240XR High-Speed Digital Modulator Appendix A
TM120 – Rev. 1.1
A
-11
<1> Latched Major
Alarm
Bit 0 = Spare
Bit 1 = Transmit Oversample PLL Lock
Bit 2 = FPGA Config Error
Bit 3 = IF Synthesizer PLL Lock
Bit 4 = External Reference PLL Lock
Bit 5 = Composite PLL Lock
Bit 6 = Symbol PLL Lock
Bit 7 = Spare
0 = Pass, 1 = Fail
<1> Latched Minor
Alarm
Bit 0 = Spare
Bit 1 = Loss Terrestrial Clock
Bit 2 = Loss Terrestrial Data
Bit 3 = FIFO Error
Bit 4 = Spare
Bit 5 = Terrestrial Framing Error
Bit 6 = Spare
Bit 7 = Spare
0 = Pass, 1 = Fail
<1> Latched Common
Fault
Bit 0 = -12 V Alarm
Bit 1 = +12 V Alarm
Bit 2 = +5 V Alarm
Bit 3 = Spare
Bit 4 = Spare
Bit 5 = Spare
Bit 6 = Spare
Bit 7 = Spare
0 = Pass, 1 = Fail
<1> Reserved TBD
<1> +5 Voltage +5 V. Implied Decimal Point. Ex: 49 = +4.9 V
<1> +12 Voltage +12 V. Implied Decimal Point. Ex: 121 = +12.1 V
<1> -12 Voltage -12 V. Implied Decimal Point and Minus Sign.
Ex: 118 = -11.8 V
<2> Reserved TBD
<2> Reserved TBD
<1> Last Rate Status 0 = Symbol Rate, 1 = Data Rate
<1> Active PIIC Slot Without Multi-PIIC Card:
1
With Multi-PIIC Card:
1 – 3