Radio Shack TRS-80, Руководство по обслуживанию, Страница: 17 / 44

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POWER SUPPLY
The MC-10 power supply utilizes an external
power pack to supply 8 VAC at 1.5 amps. This
input AC voltage is connected through the
power switch to the bridge rectifier. The MC-10
operates primarily on +5 volts, so the negative
output of the bridge is grounded to provide a
larger current capability to the positive supply.
The output from the bridge is filtered by C1 and
C5 and is connected to the +5 volt regulator.
The regulator pr5 volts at a maximum
of 1.5 amps to the digital circuitry.
A small amount of negative voltage is required
to the RS-232 output op-amp. This current is
supplied by the simple circuit composed of D2,
D3, C3, C4, and C32. This circuit operates by
using capacitor C3 for isolation from the pri-
mary bridge circuit. Then the negative voltage
is rectified by D2 and D3. The negative supply
voltage is then filtered by C4 and C32 before
being connected to U16. This is an unregulated
output. However, when coupled with the output
from the main bridges, it provides a larger dif-
ferential voltage (that is the source of the posi-
tive op-amp voltage) with no detrimental effects
on the operation of the op-amp.
VDG
The video interface function in the MC-10 is
performed by the MC6847. This is a flexible
video display generator that will produce nine
colors (eight colors and black), an alphanu-
meric display mode, and several high resolu-
tion graphics modes.
In the MC-10 the VDG is interfaced to 4K of
static RAM and the mode control inputs are
controlled by a 74LS174 register. However, the
only modes of operation which are supported
by the machine are the alphanumeric mode and
the alpha semigraphic-4 mode. Table 4 lists all
of the alphanumeric characters which may be
displayed by the VDG along with the hex code
which will produce the character. Table 2 lists
the required control bit values to produce the
MC-10 display modes.
In the MC-10 the 4K of RAM is shared between
the CPU and video display generator. This is
accomplished by providing buffers between
the address lines (U5 and U6) the data line (U7),
and synchronizing the operation of the VDG to
the CPU.
Normally the three buffers are disabled so that
the VDG address is being supplied to the RAM
and the RAM data is supplied to the VDG. How-
ever, during a CPU access to the RAM, the
three buffers are enabled and the MS* line is
used to disable the address lines of the
MC6847. This provides the CPU address to the
RAM chips and allows a CPU read or write
cycle to occur.