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User’s Manual 145
E.5 PWM Registers
There are no default values on reset for any of the PWM registers.
Table E-4. PWM Registers
PWM LSBs Register Address
PWL0R 10001000 (0x88)
PWL1R 10001010 (0x8A)
PWL2R 10001100 (0x8C)
PWL3R 10001110 (0x8E)
Bit(s) Value Description
7:6 Write
The least significant two bits for the Pulse Width Modulator count are
stored
5:1 These bits are ignored.
0 0 PWM output High for single block.
1 Spread PWM output throughout the cycle
PWM MSB x Register Address
PWM0R Address = 10001001 (0x89)
PWM1R Address = 10001011 (0x8B)
PWM2R Address = 10001101 (0x8D)
PWM3R Address = 10001111 (0x8F)
Bit(s) Value Description
7:0 write
The most significant eight bits for the Pulse-Width Modulator count
are stored
With a count of n , the PWM output will be high for n +1 clocks out of
the 1024 clocks of the PWM counter.