Rabbit 6000 User’s Manual
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314
26.3 Clocks
The wireless network port requires a 20 MHz clock input for proper operation. An external crystal can be
attached between the XTL_20MI and XTL_20MO pins, or a 20 MHz clock can be applied directly to
XTL_20MO. Note that the proper clock operation (crystal or external signal) needs to be enabled in
MSSR.
The absolute lower limit for the CPU frequency when accessing Wi-fi peripheral is 50MHz.
The interface for Wi-Fi peripheral does not run at the CPU frequency, but instead uses the 80MHz Wi-Fi
clock. This means that Wait states are usually necessary when accessing it from the Rabbit 6000. The Net-
work Port C CPU Wait Register (NCCWR) provides a five-bit field for selecting Wait states for CPU
accesses. The Network Port C DMA Wait Register (NCDWR) provides a five-bit field for selecting Wait
states for DMA accesses.
To calculate the number of Wait states required, divide 65nS by the period of the main processor clock,
round up to the next integer, and subtract two. This is the required number of Wait states, and guarantees
that the Wi-Fi cycle time of 65nS is always met.
Note that if software can guarantee that the cycle time will be met and only byte accesses will be per-
formed, a smaller number can be used for CPU Wait states. This smaller number guarantees that the mini-
mum width for the internal Wi-Fi read and write strobes will be met.
Digital
Auto Gain
Correction
VGA[4:0]
Output
Variable gain amplifier setting.
LNA[1:0]
Output
Linear amplifier setting.
Control
TXON
Output
Transmit enable.
RXON
Output
Receive enable.
LOCK
Input
Transceiver PLL lock input.
RXHP
Output
Reserved for future use, may be
used as a general-purpose output.
ANT1
Output
Antenna select enable.
ANT2
Output
Antenna select enable.
PA2G_ON
Output
2G preamplifier enable.
PA5G_ON
Output
5G preamplifier enable.
/ACT_LED
Output
Activity LED control, active low.
Management
SCLK
Output
3-wire serial clock.
SDATA
Output
3-wire serial data.
/SEN
Output
3-wire serial enable.
Table 26-1. Wireless Port Interface
Block
Section
Signal
Direction
Function
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