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Rabbit 3000 Microprocessor
7.8 System Reset
The Rabbit 3000 contains a master reset input (pin 42), which initializes everything in the
device except for the Real Time Clock (RTC). This reset is delayed until the completion of
any write cycles in progress to prevent potential corruption of memory. If no write cycles
are in progress the reset takes effect immediately. The reset sequence requires a minimum
of 128 cycles of the fast oscillator to complete, even if no write cycles were in progress at
the start of the reset. Reset forces both the processor clock and the peripheral clock in the
divide-by-eight mode. Note that if the processor is being clocked from the 32 kHz clock,
the 128 cycles of the fast oscillator will probably not be sufficient to allow any writes in
progress to be completed before the reset sequence completes and the clocks switch to
divide-by-eight mode.
During reset /CS1 is high impedance and all of the other memory and I/O control signals
are held inactive (High). After the /RESET signal becomes inactive (High) the processor
begins fetching instructions and the memory control signals begin normal operation. Note
that the default values in the Memory Bank Control Registers select four wait states per
access, so the initial program fetch memory reads are 48 clock cycles long (8 x (2 + 4)).
Software can immediately adjust the processor timing to whatever the system requires.
/CS1 is high-impedance during reset (and during power-down, when only VBAT is pow-
ered) to allow an external RAM connected to /CS1 to be powered by VBAT. This is possi-
ble because the /CS1 pin is powered by VBAT. In this case an external pull-up resistor (to
VBAT) is required on /CS1 to keep the RAM deselected during power-down. If the exter-
nal RAM connected to /CS1 is not powered by VBAT, so that any information held within
it is lost during power-down, no pull-up resistor on MEMCS1B is appropriate, as this
would add leakage (through the protection diode) to drain VBAT. The RESOUT signal,
which is High during reset and power-down, can be used to control an external power
switch to disconnect VDD from supplying VBAT.
The default selection for the memory control signals consists of /CS0 and /OE0, and
writes are disabled. This selection can also be immediately programmed to match the
hardware configuration. A typical sequence would be to speed up the clock to full speed,
followed by selection of the appropriate number of wait states and the chip select signals,
output enable signals and write enable signals. At this point software would usually check
the system status to determine what type of reset just occurred and begin normal opera-
tion.
The default values for all of the peripheral control registers are shown with the following
register listing. The registers within the CPU affected by reset are the Stack Pointer (SP),
the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP
register is set to all ones (disabling all interrupts), while all of the other listed CPU regis-
ters are reset to all zeros.
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