UMTS/HSPA Module Series
UG95 Hardware Design
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PCM_CLK
PCM_SYNC
PCM_IN/OUT
32
1
0
31
Sampling freq. = 8 KHz
32-bit data word
BCLK = 264 KHz
33
MSB
Figure 27: PCM Master Mode Timing
In general, the BitClockFrequency (BCLK) is furnished by the following expression:
BitClockFrequency=(DataW1) × SamplingFrequency
The following figure shows the reference design of PCM interface with external codec IC.
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
CODEC
Module
VDD_EXT
1K
1K
BCLK
LRCLK
DACDAT
ADCDAT
SCL
SDA
B
IA
S
MICBIAS
MIC+
MIC-
SPK+
SPK-
CLK_OUT
MCLK
Rs
NM
Figure 28: Reference Circuit of PCM Application with Audio Codec
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