5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 28 / 77
3.5. Reset
RESET_N is an asynchronous and active low signal (1.8 V logic level). Whenever this pin is active, the
modem will immediately be placed in a Power On Reset(POR) condition.
CAUTION: Triggering the RESET# signal will lead to loss of all data in the modem and the removal of
system drivers. It will also disconnect the modem from the network.
Table 7: Definition of RESET_N Pin
The module can be reset by pulling down the RESET_N pin for 200
–700 ms. An open collector/drain
driver or button can be used to control the RESET_N pin.
Host
Module
RESET_N
Reset
Logic
GPIO
67
VDD 1.8V
Reset pulse
200-700ms
R1
100k
R3
100k
R2
1k
Q1
NPN
Figure 13: Reference Circuit of RESET_N with NPN Driving Circuit
Pin No. Pin Name
Description
DC Characteristics
Comment
67
RESET_N
Reset the module
V
IH(max)
= 2.1 V
V
IH(min)
= 1.3 V
V
IL(max)
= 0.5 V
Internally pulled up to 1.8 V
with a 100 k
Ω resistor