LTE-A&5G Module Series
PCIe Card EVB User Guide
PCIe_Card_EVB_User_Guide 22 / 38
4.5. UART Interface (J601)
The PCIe Card EVB offers a UART interface: debug UART port J601. This UART interface supports
115200 bps baud rate by default and can be used for Linux console and log output.
The following figure shows the block diagram of UART on PCIe Card EVB.
J603
J602
RS-232
Level Match
3.0 V/1.8 V
Transistor Level
Translator
COM
DB9
J601
RS-232
3.0 V
U601
1.8 V
U602
DBG_TXD
DBG_RXD
DBG_RTS
DTR_TEST
Figure 13: UART Block Diagram
C2
USIM_RST
DO
(U)SIM card reset
C3
USIM_CLK
DO
(U)SIM card clock
C4
RESERVED
/
Not connected
C5
GND
/
Ground
C6
VPP
/
Not connected
C7
USIM_DATA
IO
(U)SIM card data
C8
RESERVED
/
Not connected
CD
USIM_DET
DI
(U)SIM card insertion detection
