Quectel FG50V, Проектирование аппаратного обеспечения

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Wi-Fi&BT Module Series
FG50V Hardware Design
FG50V_Hardware_Design 19 / 54
BT_EN 83 DI BT enable
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
Active high.
It is suggested to pull
down this pin with a
100 kΩ resistor.
PCM_DIN * 76 DI PCM data input
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
PCM_SYNC * 35 DI
PCM data frame
sync
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
PCM_CLK * 37 DI PCM clock
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
PCM_DOUT * 36 DO PCM data output
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
Externally pull this pin
up to VDD_IO.
BT_RTS 77 DO
BT UART request
to send V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
BT_CTS 38 DI
BT UART clear to
send
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
BT_TXD 39 DO BT UART transmit
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
BT_RXD 78 DI BT UART receive
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
BT_WAKEUP_
HOST
*
61 DO BT wakes up host
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
HOST_WAKEUP_
BT
*
60 DI Host wakes up BT
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
Externally pull this pin
down.
Coexistence Interface
Pin Name Pin No. I/O Description DC Characteristics Comment