Wi-Fi&Bluetooth Module Series
FCM561D-P_Hardware_Design
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3.4.9. Camera Interface
In the case of multiplexing, the module supports 1 camera interface. The 8-bit CMOS Image Sensor (CIS)
Digital Video Port (DVP) camera interface provides 8-bit parallel port interface to sensors, together with
main clock (MCLK), pixel clock (PCLK), horizontal SYNC (HSYNC) and vertical SYNC (VSYNC) signals.
The YUV sensor’s input will be directly fed to the hardware JPEG encoder, and the JPEG encoder output
is written to data memory directly by a dedicated DMA channel. The YUV signal format could be YUYV,
UYVY, YYUV and UVYY. HSYNC and VSYNC level could be set independently.
Table 16: Pin Definition of Camera DVP Interface
GPIO43
34
LCD_DATA4
DIO
I8080 data bit 4
GPIO44
33
LCD_DATA3
DIO
I8080 data bit 3
GPIO45
32
LCD_DATA2
DIO
I8080 data bit 2
GPIO46
67
LCD_DATA1
DIO
I8080 data bit 1
GPIO47
66
LCD_DATA0
DIO
I8080 data bit 0
Pin Name
Pin No.
Multiplexing Function
I/O
Description
GPIO27
11
DVP_MCLK
DO
DVP master clock
GPIO29
55
DVP_PCLK
DO
DVP pixel clock
GPIO30
56
DVP_HSYNC
DO
DVP horizontal sync
GPIO31
57
DVP_VSYNC
DO
DVP vertical sync
GPIO32
53
DVP_DATA0
DIO
DVP data bit 0
GPIO33
52
DVP_DATA1
DIO
DVP data bit 1
GPIO34
54
DVP_DATA2
DIO
DVP data bit 2
GPIO35
12
DVP_DATA3
DIO
DVP data bit 3
GPIO36
13
DVP_DATA4
DIO
DVP data bit 4
GPIO37
14
DVP_DATA5
DIO
DVP data bit 5
GPIO38
16
DVP_DATA6
DIO
DVP data bit 6
