LTE-A Module Series
EM06 Series Hardware Design
EM06_Series_Hardware_Design 35 / 69
The module supports 16-bit linear data format. The following two figures show respectively the timing
relationship between 8 kHz PCM_SYNC and 2048 kHz PCM_CLK in the primary mode and that between
8 kHz PCM_SYNC and 256 kHz PCM_CLK in the auxiliary mode.
P CM _CLK
P CM _SY NC
P CM _OUT
MS B
LS B
MS B
125 us
1
2
2 5 6
2 5 5
P CM _IN
MS B
LS B
MS B
Figure 19: Primary Mode Timing
P CM _CLK
P CM _SY NC
P CM _OUT
MS B
LS B
P CM _IN
125 us
MS B
1
2
32
31
LS B
Figure 20: Auxiliary Mode Timing