Quectel EG25-GL, Проектирование аппаратного обеспечения

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LTE Standard Module Series
EG25-GL_Hardware_Design 53 / 96
4.6.1 WLAN Application Interface
The module provides a SDIO 3.0 interface and control interface for WLAN design. SDIO interface
supports SDR mode, and the maximum frequency is up to 50 MHz.
As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
SDIO 3.0 specification, please comply with the following principles:
⚫
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
trace is 50
Ω ±10%.
⚫
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
⚫
It is recommended to keep matching length between SDC_CLK and SDC_DATA[0:3]/SDC_CMD less
than 1 mm and total routing length less than 50 mm.
⚫
Keep termination resistors within 15
–24 Ω on clock traces near the module and keep the route
distance from the module clock pins to termination resistors less than 5 mm.
⚫
Make sure the adjacent trace spacing is 2 times of the trace width and bus capacitance is less than
15 pF.
4.6.2 Bluetooth Application Interface *
The module supports a dedicated UART interface and a PCM interface for Bluetooth application. Further
information about Bluetooth interface will be added in the future version of this document.
4.7 ADC Interfaces
The module provides two Analog-to-Digital Converter (ADC) interfaces.
⚫
AT+QADC=0 can be used to read the voltage value on ADC0 pin.
⚫
AT+QADC=1 can be used to read the voltage value on ADC1 pin.
For more details about these AT commands, see document [2] . To improve the accuracy of ADC, the
trace of ADC should be surrounded by ground.
Table 17: Pin Definition of ADC Interfaces
Pin Name Pin No. I/O Description Comment
ADC0 45 AI General-purpose analog to digital converter
If unused, keep it open.
ADC1 44 AI General-purpose analog to digital converter