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PROJECT

TITLE

Radom.XIANG

CHECKED BY

Mountain.ZHOU

DRAWN BY

OF

A

6

5

4

3

2

1

SHEET

A

B

C

D

1

2

3

4

5

6

D

C

B

Quectel Wireless Solutions

SIZE

VER

8

8

1.0

DATE

2015/3/30

EC20 Reference Design

A2

Indicators

Indicator and Test Point

2. Refer to the document <Quectel_EC20_Hardware_Design> for more details about NET_MODE and NET_STATUS.

Notes:

1. Module STATUS is open drain output.

Reserved Test Points

Notes:
1. Both USB and debug UART interface are reserved for software debug.

3. Keep USB test points as close as possible to USB pins.

Other Design

2. USB interface can be used to upgrade firmware either.

Q802

DTC043ZEBTL

R803
2.2K

D803

Q801

DTC043ZEBTL

R802
2.2K

D802

R801
2.2K

D801

4

5

6

3

2

1

7

8

J801

D806

SD12

D807

ESD9X3.3ST5G

D805

ESD9L5.0ST5G

D804

ESD9L5.0ST5G

D808

ESD9X3.3ST5G

D809

ESD9X3.3ST5G

[1] NET_STATUS

VBAT

[1] NET_MODE

VBAT

[1] STATUS

VBAT

[1,3,8]

VBAT

[1,2]

PWRKEY

[1,2]

USB_DP

[1,2]

USB_DM

[1,2]

USB_VBUS

[1]

DBG_RXD

[1]

DBG_TXD

Quectel 

Confidential

Содержание EC20

Страница 1: ...9 RESERVED 40 RESERVED 41 I2C_SCL 42 I2C_SDA 43 RESERVED 44 ADC1 45 ADC0 46 GND 47 ANT_GNSS 48 GND 49 ANT_MAIN 50 GND 51 GND 52 GND 53 GND 54 GND 55 RESERVED 56 GND 57 VBAT_RF 58 VBAT_RF 59 VBAT_BB 60...

Страница 2: ...ware_Design and Quectel_EC20_AT_Commands_Manual AP_READY High level detection AP_READY Low level detection 4 Transistor circuits Q203 Q207 are used for level translation The necessary control circuit...

Страница 3: ..._3 0V R305 R306 1 1 207 3 0V Supply Power for PCM Codec and SD Card Close to the module VBAT pins Note VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins Power Supply Design VBAT Design Co...

Страница 4: ...ith RTS interface and the RI and DCD transistor circuit is similar with CTS interface C401 100nF 1 2 3 4 5 6 U401 ESDA6V8AV6 C403 33pF C404 33pF C402 33pF R401 22R R402 22R R403 22R R404 15K GND VPP I...

Страница 5: ...T1 23 LRCK1 26 SCL 27 SDA 28 GPIO1 IRQ1 29 DBVDD 30 DCVDD 31 MICVDD 32 MICBIAS1 8 VREF2 24 BCLK1 1 JD1 9 LOUTL P 17 HPO_R 25 MCLK 33 DGND U501 ALC5616 C505 4 7uF C504 4 7uF C503 100nF R501 0R C502 4 7...

Страница 6: ...ose an external LDO according to the active antenna to supply power VDD left Notes GNSS Antenna Circuit 2 If you design the antenna circuit with passive antenna the R603 and L603 are not needed Active...

Страница 7: ...ore than 2x line width 5 The parasitic capacitance of ESD components should be smaller than 15pF SD Design C702 33pF C701 0 1uF R702 33R R703 0R R705 0R R706 0R R707 0R R713 120K D707 ESD9X3 3ST5G R71...

Страница 8: ...put Reserved Test Points Notes 1 Both USB and debug UART interface are reserved for software debug 3 Keep USB test points as close as possible to USB pins Other Design 2 USB interface can be used to u...

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