7
Addressing
The MPAP-100 occupies a continuous 16-byte block of I/O addresses. For example, if
the base address is set to 300 hex, then the MPAP-100 will occupy address locations 300 hex to
30F hex. If the computer in which the MPAP-100 is installed is running PCMCIA Card and
Socket Services, the base address is set by the client driver. If PCMCIA Card and Socket
Services are not being used, the base address is set by the MPAP-100 enabler program.
The first four bytes of address space on the MPAP-100 contain the internal registers of
the SCC. Other Quatech architecture-specific registers occupy eight more bytes. The remainder
of the address space is reserved for future use. The MPAP-100 address map is shown in Table 2.
Reserved
Base + F
Reserved
Base + E
Receive FIFO Timeout Register
Base + D
Receive Pattern Count Register
Base + C
Receive Pattern Character Register
Base + B
FIFO Control Register
Base + A
FIFO Status Register
Base + 9
Interrupt Status Register
Base + 8
Reserved
Base + 7
Reserved
Base + 6
Configuration Register
Base + 5
Communications Register
Base + 4
SCC Control Port, Channel B
Base + 3
SCC Data Port, Channel B
Base + 2
SCC Control Port, Channel A
Base + 1
SCC Data Port, Channel A
Base + 0
Register Description
Address
Table 2 --- MPAP-100 Address Assignments
Information on the internal registers of the SCC can be found in Table 3 and Table 4 and
in the technical reference manuals available from Zilog. The other onboard registers are fully
described in subsequent chapters of this manual.
