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8.5

SCC Incompatibility Warnings 

Due to the SCC  implementation used by the MPAC-100, there are two minor

incompatibilities that the software programmer must avoid.  

8.5.1 Register Pointer Bits

In a Zilog 85230, the control port register pointer bits can be set in either channel.

With the implementation on the MPAC-100, however, both parts of an SCC control port
access must use the same I/O address.

IMPORTANT

The programmer must be certain not to mix channel

usage during the two-part access of SCC control ports.

It would be highly irregular for code to be written in

The following sequences will work:

Write Control Port A

(set pointer bits for desired register)

Read or Write Control Port A

(read or write desired channel A register)

Write Control Port B

(set pointer bits for desired register)

Read or Write Control Port B 

(read or write desired channel B register)

The following sequences will NOT work:

Write Control Port A

(set pointer bits for desired register)

Read or Write Control Port B

(read or write desired channel B register)

Write Control Port B

(set pointer bits for desired register)

Read or Write Control Port A 

(read or write desired channel A register)

8.5.2 Software Interrupt Acknowledge

The 85230's software interrupt acknowledge mechanism is not supported.  Bit 5

of Write Register 9 (Software INTACK Enable) is forced to 0.  Software must employ the
"Interrupt Without Acknowledge" interrupt method using Read Registers 2 and 3 to
process interrupts.

Quatech MPAC-100 User's Manual

27

Содержание MPAC-100

Страница 1: ...MPAC 100 RS 232 PCI SYNCHRONOUS ADAPTER for PCI Card Standard compatible machines User s Manual QUATECH INC TEL 330 434 3154 662 Wolf Ledges Parkway FAX 330 434 1409 Akron Ohio 44311 www quatech com ...

Страница 2: ...n or general misuse voids all warranty rights Although every attempt has been made to guarantee the accuracy of this manual Quatech Inc assumes no liability for damages resulting from errors in this document Quatech Inc reserves the right to edit or append to this document at any time without notice Please complete the following information and retain for your records Have this information availab...

Страница 3: ...ion or the product to which it refers at any time and without notice The authors have taken due care in the preparation of this document and every attempt has been made to ensure its accuracy and completeness In no event will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented in this document o...

Страница 4: ... 28 9 2 1 Transmit FIFO 28 9 2 Accessing the FIFOs 28 9 1 Enabling and disabling the FIFOs 28 9 FIFO Operation 27 8 5 2 Software Interrupt Acknowledge 27 8 5 1 Register Pointer Bits 27 8 5 SCC Incompatibility Warnings 26 8 4 4 Other signals are not used 26 8 4 3 Extra handshaking for channel A 26 8 4 2 Extra clock support for channel A 26 8 4 1 Receive data and clock signals 26 8 4 Support for SCC...

Страница 5: ...face Signals 49 18 4 Null modem cables 47 18 3 RING pin 22 47 18 2 SYNCA pin 10 47 18 1 5V fuse pin 9 46 18 External Connections 45 17 Receive FIFO Timeout Register 44 16 Receive Pattern Count Register 43 15 Receive Pattern Character Register Table of Contents ...

Страница 6: ......

Страница 7: ...nc and bit oriented synchronous protocols such as HDLC and SDLC The SCC also offers internal functions such as on chip baud rate generators and digital phase lock loop DPLL for recovering data clocking from received data streams Because the PCI standard does not include a direct memory access DMA interface the MPAC 100 supports only interrupt driven communications To compensate for the lack of DMA...

Страница 8: ...tructions provided by the computer manufacturer 3 Install the MPAC 100 in any empty PCI expansion slot The board should be secured by installing the Option Retaining Bracket ORB screw 4 Replace the system cover according to the instructions provided by the computer manufacturer 5 Attach and secure the cable connectors to the desired equipment 6 Turn on the power of the computer system Quatech MPAC...

Страница 9: ... for available resources to fill the boards requirements and then updates the hardware registry with an entry that allocates these resources The Syncdrive DLL and VxD can then be used to access the card 3 1 Using the Add New Hardware Wizard The following instructions provide step by step instructions on installing the MPAC 100 in Windows 98 using the Add New Hardware wizard Windows 95 uses a simil...

Страница 10: ... checkbox Insert the Quatech COM CD shipped with the card into the CD ROM drive Click the Next button 4 Windows should locate the INF file on the CD and display a dialog that looks like this Click the Next button Quatech MPAC 100 User s Manual 10 ...

Страница 11: ...5 Windows will copy the INF file from the CD and display a final dialog indicating that the process is complete Click the Finish button Quatech MPAC 100 User s Manual 11 ...

Страница 12: ...System icon inside the Control Panel folder This opens up the System Properties box 2 Click the Device Manager tab located along the top of the System Properties box 3 Double click the device group Synchronous_Communication The MPAC 100 model name should appear in the list of adapters 4 Double click the MPAC 100 model name and a properties box should open for the hardware adapter Quatech MPAC 100 ...

Страница 13: ...ick Cancel to exit without making changes 6 If changes to the automatic configuration are necessary for compatibility with existing programs uncheck the Use Automatic Settings box and double click on the Resource Type that needs to be changed Caution should be used to avoid creating device conflicts with other hardware in the system Quatech MPAC 100 User s Manual 13 ...

Страница 14: ...at values such as 3F8 hex IRQ 4 COM1 or 2F8 hex IRQ 3 COM2 etc Rather the system BIOS assigns the address and the IRQ in a plug and play fashion at boot time Software which is to use the MPAC 100 must be able to accommodate any valid assignments of these resources For Windows 95 Windows NT and OS 2 the Quatech device drivers determine what the resource assignments are and proceed accordingly In ot...

Страница 15: ...13 shows the Basic Mode display for the MPAC 100 after the Q key has been pressed In this example the MPAC 100 uses I O base address FF80 hex and IRQ 11 The hardware revision of the MPAC 100 is also displayed Pressing the N key will show similar information for all non Quatech PCI devices in the system including those devices integrated on the motherboard Quatech MPAC 100 User s Manual 15 ...

Страница 16: ...formation It cannot make changes PCI BIOS detected version 2 10 Quatech PCI adapters detected MPAC 100 Single Port Synch RS 232 Serial Adapter Hardware Revision A1 Uses IRQ 12 Base addr 1 0xD800 I O _ Numbers preceeded by 0x are hexadecimal Figure 14 QTPCI EXE Basic Mode display Figure 14 shows the Expert Mode display for the MPAC 100 after the Q key has been pressed The information from the Basic...

Страница 17: ...ces X EXIT M Change to Basic Mode Quatech PCI Configuration Information Display Software Version 1 00 B PCI BIOS details I Interrupt routing details Quatech PCI adapters detected Vendor ID 0x135c Device id 0x00F0 found in slot 0x04 on bus 0x00 Device function code 0x48 Revision ID 0x01 Hardware revision A1 PCI Class Code 0xff0000 Subsystem Vendor ID 0x135c Subsystem Id 0x00F0 INTA mapped to IRQ 12...

Страница 18: ... the Syncdrive application before the application tries to use the card Under Windows 95 98 the card is automatically configured To find the settings click the right mouse button on the My Computer icon and select Properties Select the Device Manager tab and double click the card s entry under the Synchronous Communication section Select the Resources tab to see the card s base address and IRQ Use...

Страница 19: ... for future use The MPAC 100 address map is shown in Table 2 Reserved Base F Reserved Base E Receive FIFO Timeout Register Base D Receive Pattern Count Register Base C Receive Pattern Character Register Base B FIFO Control Register Base A FIFO Status Register Base 9 Interrupt Status Register Base 8 Reserved Base 7 Reserved Base 6 Configuration Register Base 5 Communications Register Base 4 SCC Con...

Страница 20: ...t do an SCC software interrupt acknowledge by reading Read Register 2 in channel B of the SCC The value read can also be used to vector to the appropriate part of the ISR 4 Service the SCC interrupt by reading the receiver buffer writing to the transmit buffer issuing commands to the SCC etc 5 Write a Reset Highest Interrupt Under Service IUS command to the SCC by writing 0x38 to Write Register 0 ...

Страница 21: ...ecking Automatic zero insertion and deletion Automatic flag insertion between messages Address field recognition I field residue handling CRC generation and detection SDLC loop mode with EOP recognition loop entry and exit Byte oriented Synchronous Communications Internal external character synchronization 1 or 2 sync characters in separate registers Automatic Cyclic Redundancy Check CRC generatio...

Страница 22: ...eption to this rule is when accessing the transmit and receive data buffers These registers can be accessed with the two step process described or with a single read or write to the data port The following examples illustrate how to access the internal registers of the SCC Table 3 on page 26 describes the read registers and Table 4 on page 27 describes the write registers for each channel The MPAC...

Страница 23: ...and block transfer Polling transfers data without interrupts by reading the status of RR0 and then reading or writing data to the SCC buffers via CPU port accesses Interrupts on the SCC can be sourced from the receiver the transmitter or External Status conditions At the event of an interrupt Status can be determined then data can be written to or read from the SCC via CPU port accesses Further in...

Страница 24: ...ol and reset WR9 Transmit buffer WR8 Special HDLC Enhancement Register WR7 Sync character 2nd byte or SDLC Flag WR7 Sync character 1st byte or SDLC address field WR6 Transmitter initialization and control WR5 Transmit Receive miscellaneous parameters and codes clock rate stop bits parity WR4 Receiver initialization and control WR3 Interrupt vector WR2 Interrupt control Wait DMA request control WR1...

Страница 25: ...64 Baud_Rate desired baud rate for Clock_Frequency 9 8304 MHz 3FFE hex 16382 300 1FFE hex 8190 600 0FFE hex 4094 1200 07FE hex 2046 2400 03FE hex 1022 4800 01FE hex 510 9600 00FE hex 254 19200 007E hex 126 38400 Time Constant Baud Rate Table 5 time constants for common baud rates 8 3 SCC Data Encoding Methods The SCC provides four different data encoding methods selected by bits 6 and 5 in WR10 Th...

Страница 26: ...d RTxCA from the cable The W REQB signal is used to generate DMA requests between the SCC and the internal FIFOs if channel B is used for receive 8 4 2 Extra clock support for channel A The TRxCB clock output can be routed back to RTxCA as another way to use the channel B baud rate generator to derive an independent clock for the channel A receiver This is controlled by the RCKEN bit in the Commun...

Страница 27: ... desired register Read or Write Control Port A read or write desired channel A register Write Control Port B set pointer bits for desired register Read or Write Control Port B read or write desired channel B register The following sequences will NOT work Write Control Port A set pointer bits for desired register Read or Write Control Port B read or write desired channel B register Write Control Po...

Страница 28: ...re accessed through either the channel A or channel B SCC Data Port address Writing to Base 0 or Base 2 will cause a byte to be written into the transmit FIFO Reading from Base 0 or Base 2 will cause a byte to be read from the receive FIFO The FIFOs cannot be accessed if they are disabled If the FIFOs are disabled reads or writes of the SCC Data Ports access the receive or transmit register of the...

Страница 29: ...e the SCC certain bits in various SCC registers need to be set in a specific manner as shown on the following pages Because the data transfer between the FIFOs and the SCC is controlled entirely by hardware per character transmit and receive interrupts should be disabled Interrupts on transmit underruns and or special receive conditions should usually be enabled so that end of frame conditions can...

Страница 30: ...g 1 4 Assert transmit DMA request when entry location of internal FIFO is empty 0 5 WR7A Enable WR7A 1 0 WR15A Enable DMA request on transmit on DTR REQA 1 2 WR14A Disable transmit interrupts 0 1 Enable receive interrupts on special conditions only recommended or disable them completely 11 or 00 4 3 Use W REQA for receive 1 5 Set W REQA for DMA Request mode 1 6 Enable DMA request on W REQA This bi...

Страница 31: ...isable them completely 11 or 00 4 3 Use W REQB for receive 1 5 Set W REQB for DMA Request mode 1 6 Enable DMA request on W REQB This bit should be set after the other bits in WR1 are set as desired 1 7 WR1B Assert transmit DMA request when entry location of internal FIFO is empty 0 5 WR7A Enable WR7A 1 0 WR15A Disable DMA request on transmit on DTR REQA 0 2 WR14A Disable transmit interrupts 0 1 Us...

Страница 32: ...related interrupts will occur only when the MPAC 100 interrupt source is set to INTSCC See Table 10 on page 41 for details Software can read data from the receive FIFO as desired RX_PAT bit 3 Special receive pattern detected Software can read bytes from the receive FIFO until the FIFO is empty Receive data timeout with non empty FIFO Software can read at least 512 bytes from the receive FIFO RX_FI...

Страница 33: ...er which always indicates the current status of both the transmit and receive internal FIFOs Each FIFO can be checked for empty full and half full or more status at any time For details see Table 12 on page 44 9 4 4 Controlling the FIFOs The FIFO Control Register is a read write register which can be used to reset either or both the receive and transmit internal FIFOs Receive pattern detection and...

Страница 34: ...s This would seem to preclude the use of the MPAC 100 s internal FIFOs with byte oriented protocols To make the internal FIFOs more useful in byte synchronous modes the MPAC 100 can watch for a given character to be transferred consecutively a specific number of times from the SCC into the receive FIFO When this occurs the RX_PAT bit in the Interrupt Status Register see page 43 is set For instance...

Страница 35: ...interrupt is generated and RX_FIFO bit in the Interrupt Status Register see page 43 is set A character time is approximated by counting eight ticks of the bit clock To use this feature the receive clock must be output on TRxCA It can come from either an internal source or from the channel A baud rate generator While the RTxCA signal is typically used for a receive clock it is not capable of being ...

Страница 36: ... controlled sync is disabled and the SCC s SYNCA input is driven by the signal coming on pin 10 of the DB 25 connector Bit 5 LLEN Local Loopback Enable When set logic 1 this bit allows the DTE to test the functioning of the DTE DCE interface and the transmit and receive sections of the local DCE The DCE device must support local loopback for this to work When cleared logic 0 no testing occurs LLEN...

Страница 37: ...generated by the TRxC pin on channel B of the SCC When cleared logic 0 RCLK is received on pin 17 of the DB 25 connector In either case RCLK is always transmitted on pin 11 of the DB 25 connector Bit 2 TCKEN Transmit Clock Source When set logic 1 this bit allows the transmit clock TCLK to be generated by the TRxC pin on channel A of the SCC When cleared logic 0 the DTE receives TCLK on pin 15 of t...

Страница 38: ...data FIFOs will return 0 in this bit location Bit 6 Reserved always 0 Bits 5 4 INTS1 INTS0 Interrupt Source and Enable Bits These two bits determine the source of the interrupt The two sources are interrupt from the SCC INTSCC and interrupt on Test Mode INTTM Only one interrupt source can be active at a time Below is the mapping for these bits Note that FIFO related interrupts will occur only when...

Страница 39: ...n enabled The transmit data FIFO is always used with SCC channel A The receive data FIFO may be used with SCC channel A by setting RXSRC to logic 0 or with SCC channel B by setting RXSRC to logic 1 See page 29 for information on using channel B W REQA DTR REQA Transmit DMA W REQB W REQA Receive DMA RXSRC 1 RXSRC 0 Bit 0 Reserved always 0 Quatech MPAC 100 User s Manual 39 ...

Страница 40: ...ed data stream where n is the value set in the Receive Pattern Count Register This bit is set logic 1 to indicate the interrupt It remains set until cleared by writing a 1 to this bit Bit 2 RX_FIFO Receive FIFO Interrupt The receive FIFO interrupt occurs when the number of bytes held in the internal receive FIFO rises above the half full mark or when a receive FIFO timeout occurs This bit is set l...

Страница 41: ...completely full The FIFO will accept no more data from the SCC Bit 5 RXH Receive FIFO Half Full This bit is set logic 1 while the internal receive FIFO is at least half full Bit 4 RXE Receive FIFO Empty This bit is set logic 1 when the internal receive FIFO is completely empty Bit 3 Reserved always 0 Bit 2 TXF Transmit FIFO Full This bit is set logic 1 when the internal transmit FIFO is completely...

Страница 42: ... circuitry Clear this bit logic 0 to disable pattern detection See page 37 for details on the receive pattern detection feature Bit 5 EN_TO Enable Receive Timeout Set this bit logic 1 to enable the internal receive FIFO timeout Clear this bit logic 0 to disable the receive FIFO timeout See page 38 for details on the receive FIFO timeout feature Bit 4 RX_RESET Reset Receive FIFO Set logic 1 then cl...

Страница 43: ...This register can be ignored if the internal FIFOs are not being used character value 0 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 14 Receive Pattern Character Register Read Write Bits 7 0 Receive Pattern Character This is the numeric value of the character to be detected See page 37 for details on the receive character pattern detection feature Quatech MPAC 100 User s Manual 43 ...

Страница 44: ... value 0 255 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Table 15 Receive Pattern Count Register Read Write Bits 7 0 Receive Pattern Count This value is the number of times that the character stored in the Receive Pattern Character Register see page 46 must be consecutively detected for the receive character pattern detect interrupt to be generated See page 37 for details on the receive charac...

Страница 45: ...imeout Register Read Write Bit 7 X16_MODE Clock Mode If this bit is set logic 1 the data clock is divided by 16 prescaled before it is fed to the timeout circuitry This is useful for asynchronous operation If this bit is clear logic 0 the data clock is not prescaled Bit 6 Reserved always 0 Bits 5 0 Timeout Interval This is the number of character times that must elapse before a non empty internal ...

Страница 46: ... actual DSR inputs The DTE can transmit its transmit clock TCLK from the TRxCA pin of the SCC or receive TCLK on the same pin The DTE can also receive its receive clock RCLK on the RTxC pins on channels A B of the SCC or can generate RCLK using the TRxCB pin TCLK and RCLK can also be internally sourced from the channel A baud rate generator Figure 1 shows the DTE clock configuration On the left ar...

Страница 47: ...Test Mode TM condition is received from the DCE an interrupt can optionally be generated 18 1 5V fuse pin 9 Pin 9 will have a 5volt fuse tied to VDD on the other end This is compatible with the MPAP 100 series cards 18 2 SYNCA pin 10 If EXTSYNC bit 6 in the Communications Register is set to a logic 1 the SYNCA signal from the connector is used to drive the active low SYNC input of SCC channel A Th...

Страница 48: ...luded in the official RS 232 D specification Comm Reg bit 7 TM TEST MODE X 25 TRxCA pin DA TXCLK DTE X 24 N C 23 PCI STSCHG signal CE RING X 22 Comm Reg bit 4 RL RLBK X 21 DTR REQA pin CD DTR X 20 N C 19 Comm Reg bit 5 LL LLBK X 18 RTxCA pin DD RXCLK DCE X 17 N C 16 TRxCA pin DB TXCLK DCE X 15 N C 14 N C 13 N C 12 RTxCA or TRxCB pin RXCLK DTE X 11 SYNCA pin SYNCA X 10 N C 9 DCDA pin CF CD X 8 AB D...

Страница 49: ...4 Null modem cables The MPAC 100 does not use a standard asynchronous PC serial port connector pinout Typical off the shelf null modem cables cannot be used with this card Quatech MPAC 100 User s Manual 49 ...

Страница 50: ...NOTATION RXD DIRECTION From DCE This signal transfers the data generated by the DCE in response to data channel line signals received from a remote DTE data station to the DTE CIRCUIT CA REQUEST TO SEND CONNECTOR NOTATION RTS DIRECTION To DCE This signal controls the data channel transmit function of the local DCE and on a half duplex channel the direction of the data transmission of the local DCE...

Страница 51: ...ATION RING DIRECTION From DCE This signal indicates that a ringing signal is being received on the communication channel CIRCUIT CF RECEIVED LINE SIGNAL DETECT CARRIER DETECT CONNECTOR NOTATION CD DIRECTION From DCE This signal indicates to the DTE whether the DCE is conditioned to receive data from the communication channel but does not indicate the relative quality of the data signals being rece...

Страница 52: ... data CIRCUIT LL LOCAL LOOPBACK CONNECTOR NOTATION LLBK DIRECTION To DCE This signal provides a means whereby a DTE may check the functioning of the DTE DCE interface and the transmit and receive sections of the local DCE CIRCUIT RL REMOTE LOOPBACK CONNECTOR NOTATION RLBK DIRECTION To DCE This signal provides a means whereby a DTE or a facility test center may check the transmission path up to and...

Страница 53: ...drivers or other custom software all numbers in hex PCI Vendor ID 0x135C Quatech Inc PCI Device ID 0x00F0 MPAC 100 PCI Class Code Base class 0xFF Undefined Class Subclass 0x00 Interface 0x00 IRQ sourced by INTA Base address 0 0x80 bytes I O Reserved region Base address 1 0x10 bytes I O MPAC 100 I O Address Space Quatech MPAC 100 User s Manual 53 ...

Страница 54: ...lt fuse on pin 9 Transmit drivers SP211HB RS 232 compatible 600 kbps typical maximum data rate Receive buffers SP211HB RS 232 compatible 600 kbps typical maximum data rate I O Address range Sixteen byte contiguous range required determined by PCI system Interrupt levels One IRQ required determined by PCI system DMA channels Not supported by PCI bus Power requirements 115 mA at 5 volts typical Quat...

Страница 55: ...MPAC 100 User s Manual Revision 1 01 June 2001 P N 940 0090 220 ...

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