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BAUD RATE SELECTION

The 16450 or 16550 UART determines the baud rate of the serial output

using a combination of the clock input frequency and the value written to the
divisor latches. Standard personal computer serial interfaces use an input clock of
1.8432 MHz. A table of baud rates available is given in Figure 22.

2.86

56000

38400

19200

9600

7200

4800

3600

2400

0.69

2000

1800

1200

192

600

384

300

768

150

0.026

1047

110

1536

2304

ERROR BETWEEN DESIRED AND ACTUAL

VALUES (%)

DIVISOR LATCH

VALUE

DESIRED BAUD

RATE

Figure 22 --- Divisor Latch settings for common baud rates

using 1.8432 MHz input clock

Quatech ES-100D User's Manual

Содержание ES-100D

Страница 1: ...232 ASYNCHRONOUS ADAPTER CARD for ISA compatible machines User s Manual QUATECH INC TEL 330 655 9000 5675 Hudson Industrial Parkway FAX 330 655 9010 Hudson Ohio 44236 http www quatech com INTERFACE CARDS FOR IBM PC AT AND PS 2 ...

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Страница 3: ...will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented herein and in the program s accompanying this document No representation is made regarding the suitability of this product for any particular purpose Quatech Inc reserves the right to edit or append to this document or the product s to whi...

Страница 4: ...f this document and every attempt has been made to ensure its accuracy and completeness In no event will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented in this document or any software programs that might accompany this document Quatech Inc encourages feedback about this document Please sen...

Страница 5: ...icular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet...

Страница 6: ...nts and for applications involving high data rates The ES 100D is highly flexible with respect to addressing and interrupt level use The serial ports are addressed in a contiguous block that can be placed anywhere within the range of 0000 hex to FFFF hex and available interrupt levels include IRQ2 to IRQ7 IRQ10 to IRQ12 IRQ14 or IRQ15 All ports on the ES 100D share one interrupt level A special in...

Страница 7: ... each port RTS DTR CTS DSR DCD and RI See section V of this manual for connector details 1 If the default settings are correct skip to step 2 otherwise refer to sections III and IV of this document for detailed information on how to set the address and IRQ level 2 Turn off the power of the computer system in which the ES 100D is to be installed 3 Remove the system cover according to the instructio...

Страница 8: ... IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 J2 Set IRQ level here J2 QUATECH INC ES 100D 16450 16550 16450 16550 16450 16550 16450 16550 16450 16550 16450 16550 16450 16550 16450 16550 clock Figure 2 Diagram of ES 100D Quatech ES 100D User s Manual 3 ...

Страница 9: ... total of 64 contiguous bytes This is shown in Figure 3 Base Address 56 to Base Address 63 Serial 8 Base Address 48 to Base Address 55 Serial 7 Base Address 40 to Base Address 47 Serial 6 Base Address 32 to Base Address 39 Serial 5 Base Address 24 to Base Address 31 Serial 4 Base Address 16 to Base Address 23 Serial 3 Base Address 8 to Base Address 15 Serial 2 Base Address 0 to Base Address 7 Seri...

Страница 10: ...0 2 0 0 4 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 These address bits are set by the switches All other bits are considered to be zero Figure 4 Examination of a serial port base address Switch on bit 0 Switch off bit 1 Position 6 of SW2 is used to enable or disable the interrupt status register Factory default setting 0300 hex ON 2 0 0 0 1 1 2 3 4 5 6 SW2 0 0 0 0...

Страница 11: ...ignals a hardware interrupt when any port requires service The interrupt signal is maintained until no port requires service Because the ISA bus is edge sensitive this behavior forces the interrupt service routine to ensure that all ports are checked before exiting A way to do this is to poll each port until an interrupting port is found After servicing the port all ports should be checked again I...

Страница 12: ...terrupt status register reads zero before exiting or the ES 100D will be unable to signal subsequent interrupts An I O write to the interrupt status register will cause another hardware interrupt to be generated if the interrupt status register is non zero The value written is ignored and has no effect on the contents of the interrupt status register 1 if interrupt pending on Serial 1 0 1 if inter...

Страница 13: ... This page intentionally left blank 8 Quatech ES 100D User s Manual ...

Страница 14: ... be connected directly using a one to one cable as shown in Figure 10 In many applications DCEs are unnecessary and in these cases a cable called a null modem cable or modem eliminator cable is used to directly connect two DTE type devices A typical null modem cable is also shown in Figure 10 RxD TxD RTS CTS DTR DSR DCD GND 3 2 4 5 20 6 8 22 7 RI TxD RxD CTS RTS DSR DTR DCD GND 3 2 4 5 20 6 8 22 7...

Страница 15: ... 13 DTR 5 76 5 37 5 71 5 32 CTS 4 56 4 17 4 51 4 12 RTS 3 55 3 16 3 50 3 11 RxD 2 75 2 36 2 70 2 31 TxD D 25 D 78 D 25 D 78 D 25 D 78 D 25 D 78 Serial 8 Serial 7 Serial 6 Serial 5 RS 232 Signal Description 7 49 7 10 7 44 7 5 GND 22 68 22 29 22 63 22 24 RI 8 48 8 9 8 43 8 4 DCD 6 67 6 28 6 62 6 23 DSR 20 47 20 8 20 42 20 3 DTR 5 66 5 27 5 61 5 22 CTS 4 46 4 7 4 41 4 2 RTS 3 45 3 6 3 40 3 1 RxD 2 65...

Страница 16: ...4 45 46 47 48 49 50 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 51 52 53 54 55 56 57 58 59 75 76 77 78 20 21 22 23 24 25 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 D 25 connectors on the adapter cable Dashed lines delineate channels Pins 25 30 35 64 69 74 unused Figure 12 ES 100D output connectors Quatech ES 100D User s Manual 11 ...

Страница 17: ... reduce the frequency of interrupts issued to the CPU by the UART Other features of the 16450 and 16550 include Programmable baud rate character length parity and number of stop bits Automatic control of start stop and parity bits Independent and prioritized interrupts Transmit clock output receive clock input The ES 100D s serial ports are controlled by 16450 or 16550 UARTs The serial ports will ...

Страница 18: ...r 16550 only on an I O write Also notice that if address base 0 or base 1 is used with the DLAB bit from the Line Control Register set to 1 the baud rate divisor latches are accessed NOTE All figures displaying bitmapped registers are formatted such that bit 7 is the high order bit DLAB in Line Control Register must be set to access baud rate divisor latch X don t care Baud rate divisor latch MSB ...

Страница 19: ... Line Status Interrupt When set logic 1 enables interrupt on overrun parity framing errors and break indication 2 EDSSI MODEM Status Interrupt When set logic 1 enables interrupt on clear to send data set ready ring indicator and data carrier detect 3 0 reserved 4 0 reserved 5 0 reserved 6 0 reserved 7 DESCRIPTION BIT Figure 14 Interrupt Enable Register bit definitions INTERRUPT IDENTIFICATION REGI...

Страница 20: ...ed by reading the MODEM status register 4th 0 0 0 0 Transmitter Holding Register Empty Indicates the transmitter holding register is empty The interrupt is cleared by reading the interrupt identification register or writing to the transmitter holding register Indicates transmit FIFO empty for 16550 3rd 0 1 0 0 Character Timeout 16550 FIFO mode only Indicates no characters have been removed from or...

Страница 21: ...ceive FIFO reset 16550 only When set logic 1 all bytes in the receiver FIFO are cleared and the counter is reset The shift register is not cleared RRST is self clearing 1 XRST Transmit FIFO reset 16550 only When set logic 1 all bytes in the transmitter FIFO are cleared and the counter is reset The shift register is not cleared XRST is self clearing 2 DMAM DMA mode select 16550 only When set logic ...

Страница 22: ...p bits transmitted 2 PEN Parity enable Enables parity on transmission and verification on reception 3 EPS Even parity select Selects even or odd parity if parity is enabled 4 STKP EPS PEN PARITY x x 0 None 0 0 1 Odd 0 1 1 Even 1 0 1 Logic 1 1 1 1 Logic 0 STKP Stick parity Forces parity to logic 1 or logic 0 if parity is enabled 5 BKCN Break control When set logic 1 the serial output SOUT is forced...

Страница 23: ...gic 1 the RTS output is forced active to a logic 0 When cleared logic 0 the RTS output is forced inactive to a logic 1 1 OUT1 Output 1 When this bit is set logic 1 the OUT1 output is forced active to a logic 0 When cleared logic 0 the OUT1 output is forced inactive to a logic 1 Not connected on the ES 100D 2 OUT2 Output 2 When this bit is set logic 1 the OUT2 output is forced active to a logic 0 W...

Страница 24: ...longer than one full word transmission time In 16550 FIFO mode only one zero character is loaded into the FIFO and transfers are disabled until the serial data input goes to the mark state logic 1 and a valid start bit is received 4 THRE Transmitter holding register empty Indicates the transmitter holding register or FIFO 16550 is empty and it is ready to accept new data THRE is reset by writing d...

Страница 25: ...as changed state Cleared when this register is read 0 DDSR Delta data set ready Indicates the Data Set Ready input has changed state Cleared when this register is read 1 TERI Trailing edge ring indicator Indicates the Ring Indicator input has changed from a low to a high state Cleared when this register is read 2 DDCD Delta data carrier detect Indicates the Data Carrier Detect input has changed st...

Страница 26: ...nd the last read of the FIFO by the CPU was done more than four character times ago 5 Timeout interrupts are cleared when a read of the receive FIFO is done 6 The receive FIFO timeout timer is reset whenever a new character is received into the FIFO or a read of the FIFO is done When the transmit FIFO and transmit interrupts are enabled 1 The transmitter holding register empty interrupt occurs whe...

Страница 27: ... This would be done using the Line Status Register 1 The Data Ready bit will be set to logic 1 whenever there is at least one byte in the receive FIFO 2 Errors can be detected using the various error bits 3 The Transmitter Holding Register Empty bit can be used to determine when the transmit FIFO is empty 4 The Transmitter Empty bit indicates that the transmitter shift register is empty as well as...

Страница 28: ...e an input clock of 1 8432 MHz A table of baud rates available is given in Figure 22 2 86 2 56000 3 38400 6 19200 12 9600 16 7200 24 4800 32 3600 48 2400 0 69 58 2000 64 1800 96 1200 192 600 384 300 768 150 0 026 1047 110 1536 75 2304 50 ERROR BETWEEN DESIRED AND ACTUAL VALUES DIVISOR LATCH VALUE DESIRED BAUD RATE Figure 22 Divisor Latch settings for common baud rates using 1 8432 MHz input clock ...

Страница 29: ...6550 optional Interface Female high density D 78 connector or eight male D 25 connectors using optional adapter cables Transmit drivers MC1488 or compatible Receive buffers MC1489 or compatible I O Address range 0000H FFFFH Interrupt levels IRQ2 to IRQ7 IRQ10 to IRQ12 IRQ14 IRQ15 Power requirements 5 volts 450 mA 12 volts 90 mA 12 volts 90 mA 24 Quatech ES 100D User s Manual ...

Страница 30: ...S 100D requires 64 bytes of I O space Set a different address if necessary 3 The ES 100D may be defective Contact Quatech Customer Service for instructions Cannot communicate with other equipment 1 Are the cable connections correct Are the cables securely attached 2 Are the base address and interrupt level IRQ correctly set Check for address and IRQ conflicts with other devices in the system Chang...

Страница 31: ...Version 1 01 March 2004 Part No 940 0099 101 Quatech Inc ES 100 Manual ...

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