QUANTUN QP650U Plus, Руководство по обслуживанию

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QP-650U Plus Circuit Description
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The output signal from phase comparator is filtered through a low pass filter to generate a level D.C., and
the level D.C. controls oscillator frequency by controlling VCO.
VCO
The operating frequency is generated by Q100 in transmit mode and by Q101 in receive mode.
Operating frequency generate a control voltage by phase comparator to control varactor diodes so that
the oscillator frequency is consistent with the MCU preset frequency(D100
、
D101
、
D104 and D105 in
transmit mode, and D102
、
D103
、
D106 and D107 in receive mode). T/R pin is set high level in receive
mode, and low level in transmit mode. The output from Q100 and Q101 is amplified by Q103 and sent to
buffer amplifier.
Unlock detector
An unlock condition appears if low level appears at MUXOUT pin of U610. Transmission is
forbidden if this condition is detected by microprocessor.
3
．
Receiver
The receiver utilizes double conversion superheterodyne
Fig. 3 Receiver Section Configuration
Front-end RF Amplifier
The signal from antenna is amplified at RF amplifier (Q500) after passing through a transmit/receive
circuit and a band pass filter. Before passing the first mixer, the amplified signal is filtered through
another band pass filter to remove unwanted signals.
First Mixer
The signal from RF amplifier is mixed with the first local from PLL frequency synthesizer circuit at
the fix mixer (Q501) to create a 38.85MHz first IF signal. The first IF signal is then fed through a crystal
filter (XF1) to further remove unwanted signals.
IF Amplifier
The first IF signal is amplified by Q502 before passing through crystal filter after crystal filter and
then enters IF processing chip U200. The signal from U200 is mixed with the second oscillator signal