Manual for SynactiX 5EP/5EI
Advanced Chipset Features Setup
Figure-5 Advanced Chipset Features Menu
The following indicates the options for each item and describes their meaning.
Item
Option
Description
l
SDRAM CAS
3
Define the CLT timing parameter of SDRAM
Latency Time
2
l
SDRAM Cycle Time
5/7
Set DRAM Tras/Trc Cycle time is 5/7 SCLKs or 6/8
Tras/Trc
6/8
SCLKs.Tras is RAS activing time. Trc is RAS Cycle
time
l
SDRAM RAS-to-CAS
2
Set SDRAM RAS# to CAS# delay 3 SCLKs or 2
Delay
3
SCLKs
l
SDRAM RAS
2
Set SDRAM RAS# Percharge is 3 or 2
Precharge Time
3
l
System BIOS
Enabled
Besides conventional memory, the system BIOS
Cacheable
Disabled
area is also cacheable
l
Video BIOS
Enabled
Besides conventional memory, video BIOS area
Cacheable
is also cacheable
Disabled
Video BIOS area is not cacheable
l
Memory hole at
Enabled
Memory hole at 15-16M is reserved for
15M-16M
expanded ISA card
Disabled
Do not set this memory hole
BIOS Description