Quantum Design P6I440LX/ATX Legend-I, Руководство пользователя

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Chapter 2
2 - 5
,
DIMM sockets can be populated in any order. However, to take
advantage of potentially faster MA timing it is recommended to populate
sockets in order.
,
SDRAM and EDO DIMMs can be mixed within the memory array.
,
The DRAM Timing register, which provides the DRAM speed grade
control for the entire memory array, must be programmed to use the
timings of the slowest DRAMs installed.
,
Possible EDO DIMM memory size is 8MB, 16MB, 32MB, 64MB,
128MB, 256MB in each DIMM socket.
,
Possible SDRAM memory size is 8MB, 16MB, 32MB, 64MB, 128MB
in each DIMM socket.
Clear CMOS
¸
Clear CMOS :
Normal:
Note
:
You must power down the AC supply(110/220V) when you want to
clear CMOS.
Close Once
JP6
JP6