qian.mx XIAO PC, Руководство пользователя, Страница: 46 / 68

46
Here is summarization of the key differences(get from synopsys.com )
Feature DDR3 DDR3L LPDDR3
I/O Standard 1.5V SSTL 1.35V SSTL 1.2V HSUL
Common Packages
4 and 8 bit single-die
packages
4 and 8 bit single-die
packages
32-bit multi-die
packages
Command and address
bus
Single data rate with
separated command
and address
Single data rate with
separated command
and address
Double data rate with
multiplexed command
and address
Command protocol and
registers
Same as DDR3L Same as DDR3
Different to DDR3 ans
DDR3L
Output strobe timing
for 1600 speed bin
Tightly controlled by a
DLL on the DRAM chip
to /- 225ps of
clock
Tighty controlled by a
DLL on the DRAM chip
to /- 225ps of
clock
Loosely controlled (no
DLL on DRAM chip),
from 2500 to 5500 after
clock
Aproximate relative
power
X while active, Y while
in standby
85% of X while active,
85% of Y while in
standby
70% of X while active,
10% of Y while in
standby
How long does it take
to exit stanby (solf-
refresh) mode and do
a read?
512 clock cycles 512 clock cycles
112 clock cycles
for 4GB device and
DDR1600 speed
Estimated tupical
relative price
Low A little higher Highest
Typical number of
devices per memory
channel
8-32 8-32 1-4
Relevant JEDEC
standard
JESD79-3F (July 2012) JESD79-3-1A (May
2013)
JESD209-3B (August
2013)
If it was looking for
one to show you, the
first place I would look
would be...
On a DMM socketed
in a lower-end PC or
server
On a DMM socketed
in a newer laptop or
server
Soldered directly to
the PCB of a high-end
mobile phone or tablet