Chapter 3
3
-
9
Selection
60ns
as 50ns, otherwise you have to select 60ns.
•
MA Wait State
Slow
Fast
One additional wait state is inserted before the
assertion of the first MA and CAS#/RAS#
during DRAM read or write leadoff cycles.This
affects page hit, row miss and page miss cases.
Without additional wait state.
•
EDO RAS# To CAS#
Delay
2
Add a delay time between the assertion of
RAS# and CAS#
3
Without additional delay time.
•
EDO RAS#
Precharge Time
3
DRAM RAS# Precharge time=3x system
clocks.
4
DRAM RAS# Precharge time=4x system
clocks.
•
EDO DRAM Read
Burst
×
3 3 3,
×
2 2 2,
The DRAM read burst timing depends on the
type of DRAM on a per-row basis. Slower rates
may be required to support slower DRAM.
•
EDO DRAM Write
Burst
×
2 2 2,
×
3 3 3,
The DRAM write burst timing depends on the
type of DRAM on a per-row basis. Slower rates
may be required to support slower DRAM.
•
DRAM ECC
Select
ECC
Provide ECC (Error Checking and Correction)
function.
Disabled
Disable ECC / EC function.
•
CPU-To-PCI
IDE Posting
Enabled
Disabled
Enable CPU-To-PCI write posting.
Disable CPU-To-PCI write cycles to IDE.
•
Burst Write
Combinning
Enabled
Disabled
Enable PCI burst write combining.
Desable PCI burst write combining.
•
PCI-To-DRAM
Pipeline
Enabled
Disabled
Provide PCI-To-DRAM pipeline operating.
Disabled PCI-To-DRAM pipeline operating.
•
System BIOS
Cacheable
Enabled
Beside conventional memory, the system BIOS
area is also cacheable.
Disabled
The system BIOS area is not cacheable.
•
Video BIOS Cacheable
Enabled
Disabled
Beside cnventional memory, video IOS area is
also cacheable.
Video BIOS area is not cacheable.
•
Video RAM
Cacheable
Enabled
Beside conventional memory, video BIOS area
is also cacheable.
Disabled
Video BIOS area is not cacheable.
•
8 Bit I/ O Recovery
Time
1
∼
8
Define the ISA Bus 8 bit I/O operating
recovery time.
NA
8 bit I/O recovery time is not exist.
•
16 Bit I / O
Recovery Time
1
∼
4
Define the ISA Bus 16 bit I/O operating
recovery time.
NA
16 bit I/O recovery time is not exist.
•
Memory Hole At
15M-16M
Enabled
Memory Hole at 15-16M is reserved for
expanded PCI card.
Disabled
Do not set this memory hole.
•
Delayed
Содержание LEGEND-V
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Страница 19: ...Legend V 11 SpeedEasy 1 Pentium II 2 3 Del BIOS 4 SpeedEasy Pentium II 233 5 BIOS...
Страница 21: ...Legend V 13 SpeedEasy 1 Pentium II 2 3 Del BIOS 4 SpeedEasy Pentium II 233 5 BIOS...
Страница 26: ...Intorduction 1 4 This page is intentionally left blank...
Страница 54: ...AWARD BIOS Description 3 22...
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Страница 62: ...Appendix A 2 Manual Legend V Ver 1 0...