COM Express
™
PCOM‐B645VGL R0 User Manual
Copyright © PORTWELL 2020 PCOM-B645VGL
52
PME SCI
PCI Express PME SCI Enable/Disable.
★
Enabled , Disabled
Hot Plug
PCI Express Hot Plug Enable/Disable.
★
Disabled, Enabled
Advanced Error Reporting
Advanced Error Reporting Enable/Disable.
★
Enabled , Disabled
PCIe Speed
Configure PCIe Speed
★
Auto, Gen1, Gen2, Gen3
Transmitter Half Swing
Transmitter Half Swing Enable/Disable.
★
Disabled, Enabled
Detect Timeout
The number of milliseconds reference code will wait for link to
exit Detect state for enabled ports before assuming there is no
device and potentially disabling the port.
★
0
Extra Bus Reserved
Extra Bus Reserved (0‐7) for bridges behind this Root Bridge.
★
0
Reserved Memory
Reserved Memory for this Root Bridge (1‐20) MB
★
10
Reserved I/O
Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.
★
4
LTR
PCH PCIE Latency Reporting Enable/Disable
★
Enabled , Disabled
Snoop Latency Override
Snoop Latency Override for PCH PCIE. Disabled: Disable override.
Manual: Manually enter override values.
Auto(default): Maintain default BIOS flow.
★
Auto, Manual, Disabled
Snoop Latency Value
LTR Snoop Latency value of PCH PCIE
★
60
Snoop Latency Multiplier
LTR Snoop Latency Multiplier of PCH PCIE
★
1024ns, 1ns, 32ns, 32768ns,
1048576ns, 33554432ns
Non Snoop Latency Override
Non Snoop Latency Override for PCH PCIE.
Disabled: Disable override.
Manual: Manually enter override values.
Auto(default): Maintain default BIOS flow.
★
Auto, Manual, Disabled
Non Snoop Latency Value
LTR Non Snoop Latency value of PCH PCIE
★
60
Non Snoop Latency
Multiplier
LTR Non Snoop Latency Multiplier of PCH PCIE.
★
1024ns, 1ns, 32ns, 32768ns,
1048576ns, 33554432ns
Force LTR Override
Force LTR Override for PCH PCIE.
★
Disabled, Enabled
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