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Introduction 

This quick start hardware design guide is an overview of PLX Technology’s ExpressLane™ PEX 8618 PCI 
Express Switches and provides examples of how to connect to the various switch interfaces. 

1  PCI Express Link Interface 

PLX’s PEX 8618 is a 16-Lane, 16-Port 

PCI Express 2.0

 (Gen 2) compliant switch. 

PCI Express 2.0

 supports 

transfer rates of 2.5 GT/s and 5.0 GT/s per Lane. The PEX 8618 supports the required 2.5 GT/s as well as the 
optional 5.0 GT/s on its physical interface.  The Physical Media Attachment (PMA) Layer for each Lane is 
implemented as a SerDes transceiver, which is composed of a transmit path and receive path. The transmit path 
typically contains a serializer, Phase Lock Loop (PLL), and Current Mode Logic (CML) driver. The receive path 
consists of a CML Receiver buffer, Clock and Data Recovery circuit (CDR), and a de-serializer. 

As the 

PCI Express Base Specification, Revision 2.0

, continues to mature, so does its description of the Physical 

Layer Electrical sub-block. A PCI Express serial Link is described in terms of four components – Transmitter, 
Receiver, Channel, and Reference Clock. The Transmitter and Receiver elements are typically integrated into PCI 
Express silicon. The channel and Reference Clock are implemented at the system level. The PCI Express 
interoperability matrix implies that all four elements must support 5.0 GT/s for the Link to successfully run at 
5.0 GT/s. If any one element is not 5.0 GT/s-compliant, the Link will not be able to operate beyond 2.5 GT/s. 
Another important concept is that 2.5 GT/s is 

not

 a subset of 5.0 GT/s. This implies that a design targeted to meet 

5.0 GT/s might not successfully run in a 2.5 GT/s environment, if those design criteria are not met, as well. 

Figure 1

 illustrates a block diagram of a sample PCI Express Link. 

 

PLL1

CDR1

PLL2

CDR2

RefClk

Rx1

Rx2

Tx1

Tx2

Channel

Channel

Device 1

Device 2

 

Figure 1. Sample PCI Express Link Block Diagram 

 

 

PEX 8618 Quick Start Hardware Design Guide – Version 1.2 
Copyright © 2009 by PLX Technology, Inc. All rights reserved. 

1 

Содержание PEX 8618

Страница 1: ...Quick Start Hardware Design Guide Version 1 2 December 2009 Website www plxtech com Technical Support www plxtech com support Copyright 2009 by PLX Technology Inc All Rights Reserved Version 1 2 December 18 2009 ...

Страница 2: ...me without notice Products may have minor variations to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX products PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology Inc Other brands and names are the property of their respective owners Document Numbe...

Страница 3: ... and Stackup Considerations 8 2 1 PEX 8618 BGA Routing Escape and De Coupling Capacitor Placement 8 2 2 Add in Board Routing 9 2 3 System Board Routing 9 2 4 Midbus Routing 10 2 5 PCB Stackup Considerations 10 3 Non Transparent Port Function 11 4 Hot Plug Circuitry 12 5 JTAG Interface 13 6 I2 C Interface 14 7 PCI Express Lane Good Indicators 14 8 Debug Functions 14 9 PEX 8618 Strapping Balls 17 10...

Страница 4: ... 7 Figure 7 Add In Card Routing to PCI Express Gold Fingers 9 Figure 8 System Board Routing to PCI Express Slot 9 Figure 9 PCI Express Midbus Routing Example 10 Figure 10 Enable NT Function with NT Strapping Balls 11 Figure 11 Disable NT Function 11 Figure 12 SHPC Interface to PEX 8618 Block Diagram 12 Figure 13 JTAG Interface Block Diagram 13 Figure 14 I2 C Interface Block Diagram 14 Figure 15 Po...

Страница 5: ...o the quality content or adequacy of this information The information in this document is subject to change without notice Although every effort has been made to ensure the accuracy of this manual PLX shall not be liable for any errors incidental or consequential damages in connection with the furnishing performance or use of this manual or examples herein PLX assumes no responsibility for damage ...

Страница 6: ...mature so does its description of the Physical Layer Electrical sub block A PCI Express serial Link is described in terms of four components Transmitter Receiver Channel and Reference Clock The Transmitter and Receiver elements are typically integrated into PCI Express silicon The channel and Reference Clock are implemented at the system level The PCI Express interoperability matrix implies that a...

Страница 7: ...2 0 defines two de emphasis levels for devices running at 5 0 GT s 3 0 to 4 0 dB and 5 5 to 6 5 dB The desired de emphasis level for a given Link is advertised by the downstream Ports of a switch during Link recovery Endpoints and switch upstream capture this value and Set their de emphasis level accordingly Longer Links should use 6 0 dB whereas shorter Links can use the 3 5 dB level The standard...

Страница 8: ...cific Lane to 01000b 400 mVP P and the Post Cursor Emphasis Level register to 00000b no de emphasis Equation 1 PEX 8618 Transmitter Drive Level a VTRANS VDRV_LVL VPOST_EMP b VNON TRANS VDRV_LVL VPOST_EMP c VTX DE RATIO 3 5DB 20 log VNON TRANS VTRANS Example 1 Setting for Lane 0 Transmitter to 3 5 dB Port 0 SerDes Drive Level register offset B98h 4 0 01111b 750 mVpp Port 0 Post Cursor Emphasis Leve...

Страница 9: ...1 3 Reference Clock The Reference Clock is a key component to a Link that was often overlooked by system designers in first generation PCI Express systems The Reference Clock provides a 100 MHz base frequency for the PLL The PLL provides a frequency synthesis function generating the higher speed clocks required to transmit data at a rate of either 2 5 GT s or 5 0 GT s In designs that implement dig...

Страница 10: ... cm 15 in Figure 3 illustrates Reference Clock transport delay delta The PEX 8618 PEX_REFCLKn p signal is the Reference Clock Input buffer It has an internal DC biasing circuit and hence should be AC coupled from the RefClk source driver Use 0 01 to 0 1 µF capacitors 0603 or 0402 size to AC couple the Reference Clock input as illustrated in Figure 4 PLL1 CDR1 PLL2 CDR2 RefClk Rx1 Rx2 Tx1 Tx2 Chann...

Страница 11: ...ems use SSC clocking The PEX 8618 has the necessary buffering and logic required to allow the upstream port to operate using both an SSC clock and a constant frequency clock CFC source This feature is enabled when the signal STRAP_SSC_ISO_ENABLE is pulled down to VSS In order to use the SSC isolation feature the upstream port must be port 0 and its programmed port width must be x4 or x8 Enabling t...

Страница 12: ...annel is represented as a transmission line which can be modeled by a distributed series of Resistance Inductance Conductance Capacitance RLGC circuits A transmission line behaves like a low pass filter due to frequency dependent dielectric and conductor losses In PCI Express the channel contributes to amplitude loss and deterministic jitter It is important to minimize discontinuities such as vias...

Страница 13: ...er two rows of balls and Receiver differential pairs on rows three and four This means it should take two signal layers in a PCB stackup to escape the differential pairs from the BGA All Transmitters can escape on the top layer of a PCB whereas the Receiver pairs can escape on either the bottom layer or some other internal signal layer Each pair is split between two rows on the package hence the p...

Страница 14: ...ver and transmission pairs transition layers at roughly the same point In any situation the transition locations should have plenty of stitching ground vias PCI Express add in boards must be length matched within 5 mil Differential pairs for PCI Express Gen 2 add in boards should have a differential impedance of between 68 to 105 ohms 85 ohms nominal Figure 7 Add In Card Routing to PCI Express Gol...

Страница 15: ...is to determine the separation between the positive and negative conductors to achieve the needed differential impedance Additionally a PCB stackup can determine the power supply de coupling scheme for a device Parallel plane capacitance exists between a PCB s DC power and ground planes PCB reference planes have an insignificant amount of series inductance therefore their effective frequency range...

Страница 16: ... NT Port Make sure the NT port selected is NOT the same as the upstream port Method 2 Enable the NT function and configure the NT Port through the serial EEPROM when the PEX 8618 switch is powering up Method 3 Use the PEX 8618 I2 C Port 0 to enable the NT function and configure the NT Port Figure 10 illustrates how to implement the NT functions through the Strapping balls Figure 11 illustrates how...

Страница 17: ...EEPROM is essential After the PEX 8618 is powered up the state machine inside the PEX 8618 scans the number of I O expander ICs connecting to the I2 C Bus starting from Address 000h in ascending order If it cannot locate the device with Address 000h it stops the scan process After it locates the I O expander IC it automatically assigns a valid Port Number for this SHPC Figure 12 illustrates a bloc...

Страница 18: ...th 1 kohm to 5 kohm resistors Pull JTAG_TRST down to VSS with a 1 kohm to 5 kohm resistor Because the PEX 8618 JTAG clock frequency can be as high as 25 MHz a 15 ohm series terminator can be added to TCK TDI and TDO to improve signal quality Figure 13 illustrates a generic JTAG interconnection Figure 13 JTAG Interface Block Diagram PEX 8618 Quick Start Hardware Design Guide Version 1 2 Copyright 2...

Страница 19: ...the core based module The SDM function is for viewing the 20 bit Receive Bus elastic buffer exit and 20 bit Transmit Bus of each Lane of the SerDes in the PEX 8618 Two Strapping balls are used to enable either Debug mode function Pulling down the STRAP_PROBE_MODE ball enables the EPM function Pulling down the STRAP_SERDES_MODE_EN ball enables the SDM function The EPM contains 18 inputs and 38 outp...

Страница 20: ...outA17 rcvr_dat17 PEX_LANE_GOOD14 prb_outA16 rcvr_dat16 PEX_LANE_GOOD13 prb_outA15 rcvr_dat15 PEX_LANE_GOOD12 prb_outA14 rcvr_dat14 PEX_LANE_GOOD7 prb_outA13 rcvr_dat13 PEX_LANE_GOOD6 prb_outA12 rcvr_dat12 PEX_LANE_GOOD5 prb_outA11 rcvr_dat11 PEX_LANE_GOOD4 prb_outA10 rcvr_dat10 GPIO15 prb_outA9 rcvr_dat9 GPIO14 prb_outA8 rcvr_dat8 GPIO13 prb_outA7 rcvr_dat7 GPIO12 prb_outA6 rcvr_dat6 GPIO11 prb_o...

Страница 21: ...Probe Mode SerDes Debug Mode PEX_LANE_GOOD8 prb_outB4 xmit_dat4 PEX_LANE_GOOD3 prb_outB3 xmit_dat3 PEX_LANE_GOOD2 prb_outB2 xmit_dat2 PEX_LANE_GOOD1 prb_outB1 xmit_dat01 PEX_LANE_GOOD0 prb_outB0 xmit_dat0 N C at ball T6 sclk 2 rclk 2 STRAP_NT_P2P_EN trig_out trig_out STRAP_SPARE5 rcvr_dat19 GPIO27 xmit_dat19 GPIO26 xmit_dat18 ...

Страница 22: ...Ball Signal Name Functions STRAP_SERDES_MODE_EN Enable SerDes Mode Debug Function STRAP_PROBE_MODE Enable Probe Mode Debug Function STRAP_DEBUG_SEL0 Factory Test Tied High STRAP_FAST_BRINGUP Factory Test Tied High STRAP_RESERVED17 Factory Test Tied High STRAP_PLL_BYPASS Factory Test Tied High STRAP_SSC_ISO_ENABLE Enable RefClk Isolation function STRAP_RESERVED16 Factory Test Tied Low STRAP_NT_ENAB...

Страница 23: ...ed to supply transient current to the drivers It is preferred that VDD25 be implemented as a plane or partial plane either on a signal layer or main power plane layer Provide 0 1 and or 0 01 µF ceramic capacitors along with one or more 10 µF tantalum capacitors to de couple the VDD25 power balls The number of capacitors required depends upon the number of 2 5V I O balls utilized in the design and ...

Страница 24: ...s higher than 250 MHz plane capacitance provides the only effective means for de coupling Figure 15 illustrates attenuation curves measured for a PCI Express test board The plot illustrates the bare board power to ground impedance indicated in black compared with the impedance of various power planes after de coupling capacitors are populated Notice that as frequencies surpass 200 MHz the impedanc...

Страница 25: ...adding trace segments from the capacitor pads to the vias These segments add more series inductance thereby lowering the discrete capacitor LC resonant frequency Place the vias tangentially to the capacitor pads and if possible add multiple vias per pad Refer to Right the First Time A Practical Handbook on High Speed PCB and System Design by Lee Ritchie If a plane capacitor is not possible this is...

Страница 26: ... higher PCI Special Interest Group PCI SIG 3855 SW 153rd Drive Beaverton OR 97006 USA Tel 503 619 0569 Fax 503 644 6708 www pcisig com PCI Local Bus Specification Revision 3 0 PCI Bus Power Management Interface Specification Revision 1 1 PCI to PCI Bridge Architecture Specification Revision 1 1 PCI Express Base Specification Revision 2 0 PCI Express Card Electromechanical CEM Specification Revisio...

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