PEX 8509RDK Hardware Reference Manual v1.1
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© 2007, PLX Technology, Inc. All rights reserved.
2.2
PCI Express Card Edge P1
The RDK form factor is based on the PCI Express CEM 1.1 specification. The board can directly plug into
any PCI Express x4, x8, or x16 connector. All four lanes from the card edge connect to the PEX 8509’s
Port 0. The default configuration of the PEX 8509RDK sets Port 0 to be the upstream port. The card edge
provides the main source of +12V and +3.3V power, along with PERST# and REFCLK_P/N.
2.3
PCI Express Slot Connectors
The PEX 8509RDK contains four PCI Express slot connectors, which connect to the downstream ports of
the PEX 8509. All four connectors are x16 sized connectors, although the PEX 8509 connects less than
16-lanes to each of these four connectors. The PCI Express Card Electromechanical Specification 1.1
refers to this as down-shifting, and in general is not allowed to be implemented. The RDK does this for
testing purposes only; therefore, customers designing the PEX 8509 onto a platform board should size
the slot connector to match the link width of the port routing to that connector (For example, an x4 should
route to an x4 slot connector). Sizing all connectors to x16 allows any PCI Express CEM form factor card
(x16, x8, x4 or x1) to directly plug into the RDK without the use of adapters. The link between the PEX
8509 port and the plug-in card’s port will auto-negotiate to the highest common link width.
2.3.1
PCI Express Connector J1
Connector J1 is a straddle-mount (SMT), x16 PCI Express connector. Cards plugging into this slot will be
in-line with the RDK. Port 1 connects one lane (x1) to the lower four lanes of connector J1. The upper
fifteen lanes are unconnected. Power is provided to connector J1 from the ATX hard disk connector J5.
2.3.2
PCI Express Connector J2
Connector J2 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into this slot
will be perpendicular to the RDK. Port 2 connects one lane (x1) to connector J2. The upper fifteen lanes
are unconnected. Power is provided to connector J2 from the ATX hard disk connector J5.
2.3.3
PCI Express Connector J3
Connector J1 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into this slot
will be perpendicular to the RDK. Port 3 connects one lane (x1) to connector J3. The upper fifteen lanes
are unconnected. Power is provided to connector J3 from the ATX hard disk connector J5.
2.3.4
PCI Express Connector J4
Connector J4 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into this slot
will be perpendicular to the RDK. Port 4 connects one lane (x1) to connector J4. The upper fifteen lanes
are unconnected. Connector J4 is implemented as a Hot Plug controlled slot, via the PEX 8509 Hot Plug
controller and Texas Intruments power controller (see section 2.6 for more details). Power for this slot is
gated by two power FETs, which will only turn-on if a card is present in the slot (HP_PRSNT[3]# and
HP_MRL[3]# asserted).
2.4 Reference
Clock
Circuitry
Two Cypress CY28400-2 1-to-4 PCI Express clock buffers (U10 and U11) provide on-board REFCLK
distribution to the PEX 8509 and downstream slots (J1 – J4). The first CY28400-2 (U11) input is sourced
by the card edge P1. U11 provides two differential CML (current mode logic) clock outputs. One pair
drives the PEX 8509’s PEX_REFCLKP/N input. This pair is AC-coupled (C74 and C75). This is required
to block the DC information of the transmitter from the PEX 8509 clock receiver, which has on-chip
biasing and termination circuitry. The other pair drives the input of a second CY28400-2 (U10), which is
used for fan-out to the four downstream slots. The PEX 8509’s port 3 Hot Plug controller can be used to
control on the RefClk to slot J4.
