3.3
PCI Interface
The PCI interface is set up in a four-slot motherboard arrangement. Each slot has its own REQ#/GNT# pair,
which can be arbitrated by the PEX 8112. The clock buffer drives individual PCI clocks to each slot.
3.3.1
Slot Connectors
This PEX 8112RDK-F has four female PCI slots, which connect to the PEX 8112 downstream port. (Refer to
Figure 4.) Connector J3 is a straddle-mount (SMT) connector. Cards plugged into this slot are oriented parallel to
the PEX 8112RDK-F. Connectors J4, J5, and J6 are vertical-mount (SMT) connectors. Cards plugged into these
slots are oriented perpendicular to the RDK. All slots support up to 32-bit data transfers and use 5V-compatible
PCI connectors. Connector J6 is strictly a 5V connector. All four slots support up to 66-MHz transfers. Power is
provided to all connectors from the hard disk power connector, JP1.
PEX 8111
Slot 1
Up to
66 MHz
Slot 2
Up to
66 MHz
Slot 4
Up to
66 MHz
PCI
Pull-Up
Resistors
Mictor
Connectors
J6
J5
J4
J3
Slot 3
Up to
66 MHz
Figure 4. PEX 8112RDK-F Slots Diagram
3.3.2
PCI Terminations
The four PEX 8112 REQ# inputs are pulled up with 2.7K-Ohm resistors, to hold these lines for unpopulated slots.
3.3.3
PCI Clock
The PEX 8112 has only one output PCI clock, PCLKO. The Cypress Semiconductor CY2309 Zero Delay 1-to-9
clock buffer (U2) provides onboard PCI clock distribution to the PEX 8112, connectors J3, J4, J5, J6 and other
circuits. The CY2309 input is sourced by PCLKO from the PEX 8112. Depending on the voltage level of M66EN
input to PEX 8112, either 33 MHz or 66 MHz from the PCLKO of PEX 8112 is used as PCI clock source fan out
from the CY2309 to connectors J3 to J6.
3.4
PCI Express Interface
The PCI Express interface is a male card edge connector, based on the
PCI Express Card Electromechanical
(CEM) Specification, Revision 1.0a
for an x1 interface. The card edge pr12 VDC and +3.3 VDC, RefClk,
and PERST#. The PCI Express lanes are laid out as 100-Ohm, controlled-impedance, microstrip-differential pairs.
Trace length mismatch within signal pairs is not greater than 0.005".
3.4.1
RefClk
PCI Express RefClk enters the PEX 8112RDK-F through the PCI Express card edge (male) connector. RefClk is
laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch is not greater
than 0.005".
3.4.2
PERST#
PERST# is the fundamental Reset signal to the PEX 8112, from the PCI Express edge connector.
PEX 8112RDK-F Hardware Reference Manual for Board Revision 1.0, Version 1.1
© 2008 PLX Technology, Inc. All rights reserved.
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