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21 Programmable Logic Controller (PLC)
Grabber Input MVAL
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In the
PixelBusMetadataFunctionSelect
list, select from the options shown in the following image.
When you first open the Device Control dialog box, the default values for the signals as they are
transmitted from the video source are shown.
Using the BufferWM0/BufferWM1 Signals
The acquisition block tracks the on-board memory used by the image block data that has not yet been
transmitted on the Ethernet link. For example, when the data rate from the camera is higher than the
Ethernet link's available bandwidth, memory usage increases. Memory thresholds are set using eBUS
Player’s Device Control dialog box. When the memory threshold is reached, the state of the BufferWM0/
BufferWM1 signals become high. When memory usage is lower than the threshold, the state of the
BufferWM0/BufferWM1 signals become low. These signals can be used to inform the video source to
stop outputting data.
Using the Grb0AcqActive/Grb1AcqActive Signals
The Grb0AcqActive/Grb1AcqActive signals are a delayed version of the FVAL signal when the video
interface is grabbing an image block. The PLC chunk data is captured at the first video interface system
clock after the Grb0AcqActive/Grb1AcqActive signals are asserted. There is an approximate 8 to 12 pixel
clock delay between the Grb0AcqActive/Grb1AcqActive signals and the Pb0Fval/Pb1Fval signals.