PLDA XpressGX5LP-SE, Справочное руководство

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XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features
3.6 DDR3L SDRAM
The XpressGX5LP-SE features 2 independent banks of DDR3L SDRAM, each capable of addressing 4 GB in a
72-bit wide datapath. The 18 mounted devices are Micron MT41K512M8RA-125.
Figure 9: DDR3L SDRAM
The following table shows pin assignments for the DDR3L SDRAM:
Bank 0 Bank 1
FPGA Pin Signal FPGA Pin Signal
ddr3_Bank0_a00 AM17 ddr3_Bank1_a00 C22
ddr3_Bank0_a01 AR18 ddr3_Bank1_a01 E20
ddr3_Bank0_a02 AF16 ddr3_Bank1_a02 E23
ddr3_Bank0_a03 AM16 ddr3_Bank1_a03 A23
ddr3_Bank0_a04 AR19 ddr3_Bank1_a04 G20
ddr3_Bank0_a05 AG16 ddr3_Bank1_a05 F23
ddr3_Bank0_a06 AP19 ddr3_Bank1_a06 K22
ddr3_Bank0_a07 AW17 ddr3_Bank1_a07 G23
ddr3_Bank0_a08 AM19 ddr3_Bank1_a08 K21
ddr3_Bank0_a09 AT17 ddr3_Bank1_a09 D21
ddr3_Bank0_a10 AT18 ddr3_Bank1_a10 F20
ddr3_Bank0_a11 AP18 ddr3_Bank1_a11 J22
ddr3_Bank0_a12 AU18 ddr3_Bank1_a12 F21
ddr3_Bank0_a13 AW16 ddr3_Bank1_a13 E21
ddr3_Bank0_a14 AV17 ddr3_Bank1_a14 J21
ddr3_Bank0_a15 AL18 ddr3_Bank1_a15 G22
ddr3_Bank0_ba0 AL16 ddr3_Bank1_ba0 B23
Table 9: DDR3L SDRAM pin assignments