EL160.120.39 Operations Manual (020-0344-00A)
6
Generating Grayscales
The EL160.120.39 is a monochrome display but will display dithered grayscale
when driven by a suitably-equipped video controller. See Application Note
119 for more information.
Interface Information
Planar EL Small Graphics Displays (SGD) incorporate an interface that is similar
to many LCD modules. This interface is supported by a variety of off-the-shelf
chip sets which take care of all display control functionality, freeing the system
processor for other tasks. This 4-bit LCD-type video interface provides a low
cost, flexible method for controlling display brightness and power
consumption.
Video Input Signals
The end of the top line of a frame is marked by VS, vertical sync signal as
shown in Figure 2. The first pixel of each row is marked by the falling edge of
HS. The first 160 pixels, or 40 clocks, after the falling edge of HS will be visible
on the display.
The VS signal is active high. It may be independently set to a CMOS low level at
any time for longer than one frame period. During the time of VS inactivity the
display is blank. Halting VS results in a standby condition to minimize power
consumption. Input signals VID3 through VID0 contain the video data for the
screen. Pixel information is supplied from left to right and from top to bottom
four pixels at a time.
HS
VCLK
VID3-0
VS
HS
3
First Line VID Data
4
1
Pixels: w x y z
Horizontal Timing
Vertical Timing
Pixels: a b c d
5
6
9
10
7
11
8
2
Second Line VID Data
Figure 2. Video Input Timing Diagram.
Timing is compatible with LCD graphics controllers such as the SED 1335.
