Pioneer TS4, Руководство по обслуживанию, Страница: 57 / 71

57
TS4
External interrupts
Pin In/Out Function
Interrupt0-1 in Interrupt.
System services
Pin In/Out Function
in
in
in
in
in
Err
in/out, out
ClockIn
SpeedSelect0-1
notRST
CPUAnalyse / TrigIn
CPUReset
ErrorOut / TrigOut
1
System input clock - PLL or TimesOneMode.
PLL speed selector.
System reset.
Error analysis / External trigger input to DCU.
Soft reset for analyzing from OS-Link.
Error indicator / Signal to trigger external debug circuitry (e.g. LSA).
External memory interface
Pin In/Out Function
out
in/out
out
in
out
in
out
out
out
out
out
out
in
out
Address bus.
Data bus. MemData0 is the least significant bit (LSB) and MemData31 is
the most significant bit (MSB).
ReadnotWrite strobe.
Direct memory access request.
Direct memory access granted.
Memory cycle extender.
CAS strobes - bytes 0-3 or banks 0,1.
RAS strobes - banks 0,1.
Chip select strobe for ROM in bank3.
Output enable strobe - banks 0-3.
Byte enable strobes - banks 0-3.
Chip select strobe for memory in bank 2.
Boot from ROM or from link.
Processor clock.
MemAddr2-23
MemData0-31
MemRdnotWr
MemReq
MemGrant
MemWait
notMemCAS0-3
notMemRAS0-3
notMemCSROM
notMemOE
notMemBE0-3
notMemCS2
BootSource0-1
ProcClockOut
1 This pin is tri-stated during reset and then sampled at the end of the reset to determine whether the OS-Link is active and to determine the
function of the shared CPUAnalyse / TrigIn and the ErrorOut / TrigOut . If the ErrorOut pin is sampled high (i.e at VDD) then the DCU
signals (
TrigIn
and
TrigOut
) are selected and a low value indicates OS-Link signals (i.e.
CPUAnalyse
,
ErrorOut
) are to be used.