DEH-P780MP/XN/UC
87
5
7
8
5
6
7
8
C
D
F
A
B
E
S1D13702F00A100
HVDD
VSS
LVDD
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
XWAIT
HVDD
VSS
LVDD
GCLKRA
GCLKBB
GCLKBA
GCLKGB
GCLKGA
GCLKRB
HVDD
VSS
LVDD
PDA[0]
PDA[1]
PDA[2]
PDA[3]
PDA[4]
PDA[5]
LP1A
LP1B
LP2A
LP2B
DIS1A
DIS1B
DIS2A
DIS2B
GPRO[2]
GPRO[4]
GPRO[5]
GPRO[6]
GPRO[3]
GPRO[0]
GPRO[1]
LVDD
VSS
HVDD
XCD
XCG
XRESET
CLK
MPUSEL
SWAP
XCS
RS
XRD
XWR
XBHE
XA0
DCLK
YD
XINT
GPSO
TESTEN
SECS
SECK
SEDO
SEDI
PDA[7]
PDA[6]
GPRO[7]
1
20
40
21
41
60
80
61
-
Block Diagram
-
Pin Layout
MPUSEL
SWAP
HVDD
LVDD
VSS
TESTEN
PDA[7:0]
3.3 V
1.8 V
XRESET
DCLK
XCD
CLK
XCG
OSC
General
Purpose
GPSO
RS
XBHE
XA0
XCS
XRD
XWR
XWAIT
XINT
Parallel
GCLKBA
GCLKGA
GCLKRA
DIS2A
DIS1A
LP1A
YD1
GCLKBB
GCLKGB
GCLKRB
DIS2B
DIS1B
OLED
I/F
Superposition
Control
Bit
Processing
Layer1
Layer2
YD2
REG
GPRO[7:0]
LP2A
LP1B
LP2B
GPCK
Serial
I/F
512 byte
Color Palette
72K byte
Frame Memory
Memory
Mediation
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9
2
8
9
4
2
9
8
TEL 13942296513
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4
2
9
8
0
5
1
5
1
3
6
7
3
Q
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