102
SDV-P7
Pin No.
Pin Name
I/O
Function and Operation
88
DACCK
O
DAC clock output
89
LRCK
O
LR clock output
90
SRCK
O
Bit clock output
91
VDD-91
Power supply
92-94
ADOUT0-2
O
Audio data output
95
VSS-95
GND
96
CLKMON
O
Clock monitor
97
CLK121
I
121.5MHz clock input
98
VDD-98
O
Power supply
99
CLK27
I
27MHz clock input
100
PLLAVDD
PLL analog power supply
101
TCPOUT
O
OPEN
102
PLLAVSS
O
OPEN
103
CKIO
I
81MHz clock select
104
PLLVDD
PLL
105
LVDD-105
Lch power supply
106
CLK81
I
81MHz clock input
107
VSS-107
I
GND
108
APLLVDD
Analog PLL power supply
109
ATCPOUT
O
OPEN
110
EXTCK
I
Outside clock output
111
VDD-111
Power supply
112
APLLAVDD
Analog PLL audio power supply
113
AVROUT
OPEN
114
AVCOIN
GND
115
APLLAVSS
Analog PLL audio GND
116
VREFB
I
DAC reference input
117
IREFB
I
DAC resistance terminal for bias current setting
118
COMPB
I
DAC capacity connection terminal for stabilization
119
VBOUT
O
C analog output
120
AVDD1
Analog power supply
121
VREFG
I
DAC reference input
122
IREFG
I
DAC resistance terminal for bias current setting
123
COMPG
I
DAC capacity connection terminal for stabilization
124
VGOUT
O
Cb composite analog output
125
AVSS1
Analog GND
126
VREFC
I
DAC reference input
DAC resistance terminal for bias current setting
DAC capacity connection terminal for stabilization
Cr C analog output
Analog power supply
DAC reference input
DAC resistance terminal for bias current setting
DAC capacity connection terminal for stabilization
Y analog output
Analog GND
Not used
Audio PLL test mode
Clock mode select
139
PLLTEST
PLL test
140,141
TESTSEL0,1
O
Test signal
142
DCTEST
I
DC test mode
143
XVSYNCO
I/O
Vertical sync input/output
144
XHSYNCO
I/O
Horizontal sync input/output
145
VCLK
O
Video data clock
146
LVDD-146
Lch power supply
147-150
VD0-3
O
Video data bus
151
VSS-151
GND
152-155
VD4-7
O
Video data bus
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