DV-565A-S
82
1
2
4
1
2
4
C
D
F
A
B
E
Internal peripherals
Front-end &
link interface
DMA
Central
command port
bl
o
ck m
o
ve
D
ebug
MP
E
G
MP
E
G
DMAs
Communications
arbiter
CPU
(C2+)
Clock
generator
Refill
control
RID
Diagnostic
controller
DCache
SRAM
ICache
TAP
CPU arbiter
Cache sub-system
ST20 arbiter and memory controller
I/F
SDRAM
block move
CD FIFOs
Command I/F
SDRAM arbiter (LMC)
OSD, SP
decoder
Video
filtering
DENC
Programmable
CPU interface
(EMI)
Shared
SDRAM
interface (SMI)
Video
decoder
and mixing
JTAG
debugging
interface
Analog/digital
Video output,
480i/480p
16, 32, 64 or
128-Mbit
SDRAM
Ext peripherals:
flash, additional
DRAM SDRAM
DVD
2 UARTs,
2 I
2
C-SSCs,
IR transceiver
MAFE interface
Audio &
Karaoke
Low power
mode
Audio
in/out
¶
Block Diagram
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