DV-2850-S
75
5
6
7
8
5
6
7
8
C
D
F
A
B
E
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin Name
FWD
REV
V CC 2
VLO –
VLO +
VO4 +
VO4 –
VO3 +
VO3 –
VO2 +
VO1 –
VO1 –
VO1 +
VCCP1
VCCS
VIN1 +
VIN1 –
VIN1
VIN2 +
VIN2 –
VIN2
VIN3 –
VIN3
VO_OP
VIN–OP
VIN+OP
REG_IN
REG_OUT
VREF_OUT
VREF_IN
VIN4
VIN4 –
MUTE234
MUTE1
VCONT
S_GND
Pin Descriptions
Loading output direction switching (FWD). Loading system logic input.
Loading output direction switching (REV). Loading system logic input.
Channels 3, 4, and loading power stage power supply
Loading output (–)
Loading output (+)
Channel 4 output (+)
Channel 4 output (–)
Channel 3 output (+)
Channel 3 output (–)
Channel 2 output (+)
Channel 2 output (–)
Channel 1 output (–)
Channel 1 output (+)
Channel 1 and 2 power stage power supply
Signal system power supply
Channel 1 input. Input operational amp input.
Channal 1 input. Input operational amplifier – input.
Channel 1 input. Input operational amplifier output.
Channal 2 input. Input operational amp input.
Channel 2 input. Input operational amplifier – input.
Channel 2 input. Input operational amplifier output.
Channel 3 input. Input operational amplifier – input.
Channal 3 input. Input operational amplifier output.
Operational amplifier output
Operational amplifier – input
Operational amp input
Regulator error amplifer output. Connect this pin to the base of the external pnp
transistor.
Regulator error amplifier input (+).
VREF amplifier (voltage follower) output.
VREF input. Apply the external reference voltage to this pin.
Channal 4 input. Input operational amplifier output.
Channal 4 input operational amplifier – input.
Controls the on/off state of channals 2, 3, and 4.
Channal 1 output on/off control
Loading block output high–level voltage setting
Signal system ground
Содержание DV-2850-S
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Страница 79: ...DV 2850 S 79 5 6 7 8 5 6 7 8 C D F A B E ...