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DJM-400
84
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Width
Pins
Address
8
19:2
17 through 0
The ED7 - ED0 pins are muxed with general-purpose input/output 1 (GP1) pins.
The EMIFDIS bit in the DEVCFG register controls the function of these muxed pins, EMIF is
default.
No.
Pin Name
I/O
Pin Function
EMIF-ADDRESS
39
EA2
O
External address (word, half-word, and byte address)
The EMIF adjusts the address based on memory width:
40
EA3
41
EA4
42
EA5
43
EA6
44
EA7
46
EA8
49
EA9
51
EA10
58
EA11
61
EA14
62
EA13
63
EA16
64
EA12
65
EA15
66
EA18
68
EA17
69
EA19
EMIF-DATA
75
ED6/GP1 [6]
I/O
76
ED7/GP1 [7]
79
ED4/GP1 [4]
80
ED5/GP1 [5]
81
ED3/GP1 [3]
82
ED2/GP1 [2]
83
ED1/GP1 [1]
84
ED0/GP1 [0]
MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1)
1
GP0 [4](EXT_INT4)
/AMUTEIN1
I/O
General-purpose input/output 0 pin 4 and external interrupt 4 (default) or McASP1 mute input.
14
AXR0 [1]/AXR1 [14]
I/O
McASP0 TX/RX data pin 1 or McASP1 TX/RX data pin 14
18
AXR0 [0]/AXR1 [15]
McASP0 TX/RX data pin 0 or McASP1 TX/RX data pin 15
88
AFSR1
I/O
McASP1 receive frame sync or left/right clock (LRCLK)
89
ACLKR1
I/O
McASP1 receive bit clock
91
AXR0 [15]/AXR1 [0]
I/O
McASP0 TX/RX data pin 15 or McASP1 TX/RX data pin 0
92
AXR0 [14]/AXR1 [1]
McASP0 TX/RX data pin 14 or McASP1 TX/RX data pin 1
94
AXR0 [13]/AXR1 [2]
McASP0 TX/RX data pin 13 or McASP1 TX/RX data pin 2
95
AXR0 [12]/AXR1 [3]
McASP0 TX/RX data pin 12 or McASP1 TX/RX data pin 3
97
AXR0 [11]/AXR1 [4]
McASP0 TX/RX data pin 11 or McASP1 TX/RX data pin 4
98
AXR0 [10]/AXR1 [5]
McASP0 TX/RX data pin 10 or McASP1 TX/RX data pin 5
99
AXR0 [9]/AXR1 [6]
McASP0 TX/RX data pin 9 or McASP1 TX/RX data pin 6
100
AXR0 [8]/AXR1 [7]
McASP0 TX/RX data pin 8 or McASP1 TX/RX data pin 7
102
ACLKX1
I/O
McASP1 transmit bit clock
105
AMUTE1
O
McASP1 mute output
GP0 [13], along with GP0 [0] and AMUTE1, function as boot mode configuration pins at device
reset.
107
AFSX1
I/O
McASP1 transmit frame sync or left/right clock (LRCLK)
110
AHCLKX1
I/O
McASP1 transmit high-frequency master clock
112
AHCLKR1
I/O
McASP1 receive high-frequency master clock
Содержание DJM-400 - CDJ-400 Package
Страница 34: ...DJM 400 34 1 2 3 4 1 2 3 4 C D F A B E 3 13 VRSW ASSY 2 3 E 2 3 VRSW ASSY DWX2520 E 2 3 E 3 3 ...
Страница 35: ...DJM 400 35 5 6 7 8 5 6 7 8 C D F A B E E 2 3 E 3 3 E 3 3 LEVEL METER M LEVEL METER LEVEL METER2 ...
Страница 36: ...DJM 400 36 1 2 3 4 1 2 3 4 C D F A B E 3 14 VRSW 3 3 FADER and CFVR ASSYS E 3 3 VRSW ASSY DWX2520 E 3 3 ...
Страница 91: ...DJM 400 91 5 6 7 8 5 6 7 8 C D F A B E ...