61
DEH-P400,P4000,P4050
-
Pin Functions (UPD63710GC)
Pin No.
Pin Name
I/O
Function and Operation
1
GND
Logic circuit GND
2
HOLD
I/O
Defect detection output
3
MIRR
I/O
MIRR output
4
FOK
O
RFOK signal output
5
rst
I
Reset signal input
6
A0
I
Command/parameter identification signal input
7
stb
I
Data strobe signal input
8
sck
I
Clock signal input for serial data input/output
9
SO
O
Serial data and status signal output
10
SI
I
Serial data input
11
VDD
Positive power supply terminal to logic circuit
12
DA.VDD
Positive power supply terminal to D/A converter
13
NC
Not used
14, 15
DA.GND
D/A converter GND
16
NC
Not used
17
DA.VDD
Positive power supply terminal to D/A converter
18
R+
O
Right channel audio data output
19
R-
O
Right channel audio data output
20
L-
O
Left channel audio data output
21
L+
O
Left channel audio data output
22
X.VDD
Positive power supply terminal to crystal oscillation circuit
23
xtal
O
Crystal oscillator connect pin
24
XTAL
I
Crystal oscillator connect pin
25
X.GND
Crystal oscillation circuit GND
26
VDD
Positive power supply terminal to logic circuit
27
EMPH
O
Output pin for the pre-emphasis data in the sub-Q code
28
FLAG
O
Flag output pin to indicate that audio data currently being output consists
of noncorrectable data
29
DIN
I
Serial data input to internal DAC
30
DOUT
O
Serial audio data output
31
SCKIN
I
Serial clock input to internal DAC
32
SCKO
O
Audio data that is output from DOUT changes at rising edge of this clock
33
LRCKIN
I
LRCK signal input to internal DAC
34
LRCK
O
Signals to distinguish the right and left channels of the audio data output
from DOUT
35
WDCK
O
Output double the frequency of LRCK
36
TX
O
Digital audio interface data output
Logic circuit GND
O
Oscillator clock buffering output
I
Status of the pin is output at Bit 5 of the status output
Positive power supply terminal to logic circuit
O
EFM synchronous detection signal
O
Frame synchronous signal of XTAL-system
O
Frame synchronous signal of PLL-system
O
Monitor pin of bit clock
Logic circuit GND
O
Output pin for indicating the C1 error correction results
O
Output pin for indicating the C1 error correction results
O
Output pin for indicating the C2 error correction results
49
C2D2
O
Output pin for indicating the C2 error correction results
50
C2D3
O
Output pin for indicating the C2 error correction results
51
VDD
Positive power supply terminal to logic circuit
52
PACK
O
CD-TEXT PACK synchronous signal
53
TSO
O
CD-TEXT data serial output
54
TSI
I
CD-TEXT control parameter serial input
55
tsck
I
CD-TEXT serial clock input
56
TSTB
I
CD-TEXT parameter strobe signal input
57
GND
Logic circuit GND
58
TEST
I
Test pin
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