Pioneer CMX-3000, Руководство по обслуживанию

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80
CMX-3000, CU-V163
Pin Function (3/4)
Pin
No
Port Name Pin Name I/O Function
105 CKE/ PTK [5] CKE O CK enable (SDRAM)
106 XRAS3L/PTJ [0] RAS3L O RAS3L (SDRAM)
107 XRAS2L/PTJ [1] DSPRST OUT: high Reset output for DSP (H: reset)
108 XCASLL/ XCASL/ PTJ [2] CASL O CASL (SDRAM)
Power supply (0V) for I/O
Power supply (0V)
Power supply (1.8V)
Power supply (1.8V) for PLL1
Power supply (0V) for PLL1
Power supply (0V) for PLL2
Power supply (1.8V) for PLL2
Power supply (0V)
Power supply (0V)
Power supply (1.8V)
Power supply (3.3V) for I/O
109 VssQ VssQ
−
110 XCASLH/ XCASU/ PTJ [3] FPGARST OUT: high Reset output for FPGA (H: reset)
111 VccQ VccQ
−
112 XCASHL/ PTJ [4] CDRST B OUT: high TC9495F reset B (H: reset)
113 XCASHH/ PTJ [5] CDRST A OUT: high TC9495F reset A (H: reset)
114 XDACK0/ PTD [5] DACK0 O FPGA DMA acknowledge 0
115 XDACK1/ PTD [7] DACK1 O FPGA DMA acknowledge 1
116 XCAS2L/ PTE [6] LOADIN A OUT: high Loading motor control A (Lead-in direction moves with Low)
117 XCAS2H/ PTE [3] LOADOUT A OUT: high Loading motor control A (Eject direction moves with Low)
118 XRAS3U/ PTE [2] MUTE B OUT: high Audio output stage mute B (H: mute ON)
119 XRAS3U/ PTE [1] MUTE A OUT: high Audio output stage mute A (H: mute ON)
120 TDO/ PTE [0] TDO OTHER
−
121 XBACK BACK O NC
122 XBREQ BREQ I Pull up
123 XWAIT WAIT I Pull up
124 XRESETM RESETM I Pull up
125 XADTRG/ PTH [5] FPGA DONE IN: pull-up DONE for FPGA configulation
126 XIOIS16/ PTG [7] RY/ XBY IN: pull-up Connect to flash ROM
127 XASEMD0/ PTG [6] ASEMD0 OTHER
−
128 XASEBRKAK/ PTG [5] ASEBRKAK OTHER
−
129 PTG [4] FPGA XINIT IN: pull-up INIT for FPGA configulation
130 AUDATA [3]/ PTG [3] AUDATA [3] OTHER
−
131 AUDATA [2]/ PTG [2] AUDATA [3] OTHER
−
132 Vss Vss
−
133 AUDATA [1]/ PTG [1] AUDATA [1] OTHER
−
134 Vcc Vcc
−
135 AUDATA [0]/ PTG [0] AUDATA [0] OTHER
−
136 XTRST/ PTF [7]/ PINT [15] TRST OTHER
−
137 TMS/ PTE [6]/ PINT [14] TMS OTHER
−
138 TDI/ PTE [5]/ PINT [13] TDI OTHER
−
139 TCK/ PTF [4]/ PNT [12] TCK OTHER
−
140 XIRLS [3]/ PTF [3]/ PINT [11] LPS1 A IN: pull-up Loading switch A (switch ON: Low)
141 XIRLS [2]/ PTF [2]/ PINT [10] LPS2 A IN: pull-up Loading switch A (switch ON: Low)
142 XIRLS [1]/ PTF [1]/ PINT [9] LPS1 B IN: pull-up Loading switch B (switch ON: Low)
143 XIRLS [0]/ PTF [0]/ PINT [8] LPS2 B IN: pull-up Loading switch B (switch ON: Low)
144 MD0 MD0 I Pull down Clock mode setting
145 Vcc-PLL1 Vcc-PLL1
−
146 CAP1 CAP1
−
C External capacitance pin for PLL1
147 Vss-PLL1 Vss-PLL1
−
148 Vss-PLL2 Vss-PLL2
−
149 CAP2 CAP2
−
C External capacitance pin for PLL2
150 Vcc-PLL2 Vcc-PLL2
−
151 AUDCK/ PTH [6] AUDCK OTHER
−
152 Vss Vss
−
153 Vss Vss
−
154 Vcc Vcc
−
155 XTAL XTAL O 12MHz ceramic resonator
156 EXTAL EXTAL I 12MHz ceramic resonator