Pioneer AVR-W6100 UC, Руководство по обслуживанию

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AVR-W6100/UC
A
B
C
D
5 6 7 8
5 6
7
8
67
99
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90
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10
11
12
13
14
15
16
17
18
19
20
30
1
2
3
4
5
6
7
8
9
R Signal Out
D/A Bias 3
D/A Bias Out
Analog Vss
G Signal Out
Main A/D Verf.Low
R
IN1
GIN1 B
IN1
Main A/D Verf.High
A/D Bais.5
A/D Verf.Low
C.Video Signal IN2
A/D Vref.High
R
IN2
GIN2 B
IN2
Reset IN
Bus Data I/O
Bus Serial Clock IN
RGB Over lay Cont.IN
Digital VDD(2.5V)
OSD Blank IN
OSD R IN
X'tal IN
X'tal OUT
OSD G IN
OSD B IN
Digital Vss
C.Video Signal IN1
Buffer Vss
A/D A/D A/D
A/D 8bit
XO
Digtal
PLL
Sub Timing
Pulse Gene
H/V Sep
NTSC:2line
Y/C Sep
PAL:LPF/BPF
Color
Decode
2M
Memory
PIP
Process Matrix
Control
NGOE
CPV
CX
CPH
POLS
STV1
STV2
STH1
STH2
POLC
FNAVI
CLMPO
γ
Process
Signal
Polarity
D/A
OSD
NDSH
NDSV
SCKE
Bus
Inter
Face
Inter
Face
Color
Palette
Output
Switch
Y U V
C
R
G
B
C.Sync1
C.Sync2
VD2
HD2
x 4
HD2
VD2
C.Video
RGB
Side
OSD
Side
Side
D/A
8bit
10bit
VCO
48M
PD1/PD2
Analog
1/ 5
1/ 2
1/ 6
Ped.Clamp(63.5LSB)
1/ 2
Analog
PLL
31
32
33
34
35
36
21
22
23
24
25
26
27
28
29
100
101
102
103
104
105
106
107
108
109 110 111 112 113 1 1 4 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Analog Vss
Analog VDD(2.5V)
Analog VDD(2.5V)
Buffer Vss
Buffer VDD(3.5V)
Digital VDD(2.5V)
Clock D/A Bias
Clock D/A Vref.
Digital VDD(2.5V)
D/A
42 M
13. 5 M
27M
Vss
Vss
Vss
Vss
Vss
Vss Vss
VDD
VDD
VDD VDD
VDD
R G B
Analog Vss
Analog VDD(2.5V) Analog VDD(2.5V)
Analog Vss
Digital Vss
DRAM Vss
DRAM VDD (DR.2.5V)
D.RAM Test
Dispaly Mute
Test mode2
Test mode3
Digital VSS
Digital VDD(2.5V)
Digtal Vss
Buffer VDD(3.3V)
Buffer Vss
D/A Bias 1
Common Polality Out
Analog VDD(2.5V)
Ext.Clamp Bias Out
D/A Bias.4
B.Signal Out
Vref.IN
PLL Digital VDD(2.5V)
PLL Analog VDD(2.5V)
H.PLL Filter Out
H.PLL Filter IN
A.G.S.1
PLL Analog Vss
PLL Digital Vss
Analog VDD(2.5V)
A/D Bais.6
Analog Vss
CK D/A Analog VDD(2.5V)
Sub PLL Filter
Sub PLL Analog VDD(2.5V)
Sub PLL Digital VDD(2.5V)
Sub PLL IN
A.G.S.2
Sub PLL Analog Vss
Sub PLL Digital Vss
C.Video Sync IN
DRAM Vss
DRAM VDD(DR.2.5V)
Buffer VDD(3.3V)
Gate Enable Out
Gate Clock Out
H.Sampling Start1
H.Sampling Start2
Signal Polality Out
Output Signal Clamp Pulse
Gate Scan Start 1
Gate Scan Start 2
H.Sampling Latch Select
H.Sampling Clock
Analog Vss
VCO Moniter
H.Sync IN
V.Sync IN
RGB 2 C.V.Sync IN
Ext.PLL Clock
Ext.PLL H.ref.
Ext.PLL Select
OSD Clock Out
OSD V.Sync Out
OSD H.Sync Out
T
e
st
9
Te
s
t
1
0
Te
s
t
1
1
Te
s
t
1
2
Te
s
t
1
3
Te
s
t
1
4
Te
s
t
1
5
Te
s
t
1
7
Te
s
t
1
8
Te
s
t
1
9
Te
s
t
2
0
Te
s
t
2
1
Te
s
t
2
2
Te
s
t
2
3
Te
s
t
2
4
Te
s
t
2
6
Te
s
t
2
7
Te
s
t
2
8
Te
s
t
2
9
Te
s
t
3
0
Te
s
t
1
6
Te
s
t
25
Vss
VCOM
VDD
Vss
VDD
VDD
Vss
VDD
VDD
AGS
VCO
54M
PC1,CP1
1/ 4
1/ 2
Li m
Vss VDD Vss AGS1
1 / 3048
CP1/CP2
H/V Sep
PLL
8. 0 M
9. 6 M
4. 8 M
VDD
HD1
VD1
CKP
HREF
CKPSEL
1 / 3050
REFO
Red
Green
Blue
Vss
Vss
Vss
VDD
VDD
VDD
VCO Monitor
Vss
VDD
Nagative ACK Out
ACK
Clock D/A Out
CK D/A Analog Vss
Test mode1
Test mode0
C.Video Signal IN1 Cl amp Out1
C.Video Signal IN2 Cl amp Out1
Vss
Ped.Clamp
(8LSB)
Ped.Clamp
(8LSB)
Cont./Bright
RGB
OSD
Cont./Bright
C.Video
VDD
Mute
VDD VDD VDD Vss
T
e
st
8
T
e
st
6
T
e
st
5
T
e
st
4
T
e
st
3
T
e
st
2
T
e
st
1
T
e
st
0
Te
s
t
7
D/A
D/A
D/A
Main Timing
Pulse Gene
*TC90A64AF