70
AVD-W6000
Pin No.
Pin Name
I/O
Function and Operation
28
CPV
O
Gate driver clock signal
29
NGOE3
O
Gate driver enable signal 3
30
NGOE2
O
Gate driver enable signal 2
31
NGOE1
O
Gate driver enable signal 1
32
STV2
O
Gate driver scanning start signal 2
33
VDD
Power 5V
34
XCKE
I
Forced nonstandard switching setting
35
SVSEP
I
Vertical synchronization switching
36
TST1
I
Test terminal 1
37
TST2
I
Test terminal 2
38
TST3
I
Test terminal 3
39
TST4
I
Test terminal 4
40
XCKI
I
Test terminal 5
41
SIZE
I
Number of horizontal pixels switching setting
42
VSS
GND
43
OSCO
O
Oscillation output
44
OSCI
I
Oscillation input
45
VDD
Power 5V
46
LPFO
O
Test output terminal
47
LPFI
I
Mask switching terminal
48
GND
GND
49
VDD
Power 5V
50
PDOS
O
Phase comparison signal output
51
TSTD
I
Vertical sequence switching setting
52
VSS
GND
53
STH1
O
Horizontal sampling start signal 1
54
STH2
O
Horizontal sampling start signal 2
55
VSS
GND
56
HDIR
O
Horizontal sampling direction control signal
57
CX
O
Horizontal sampling latch switching signal
58
VDD
Power 5V
59
CPH
O
Horizontal sampling clock signal
60
VSS
GND
61
SCK
O
External output horizontal clock signal
62
VSS
GND
63
SCKE
I
External output horizontal clock control signal
64
VDD
Power 5V
33
48
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