phyCOREi.MX27
36
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PHYTEC Messtechnik GmbH 2011 L-710e_5
7.5.1
Setting the EEPROM Lower Address Bits
(J13, J15, J16)
The 32 KB I²C EEPROM populating U12 on the phyCORE-module has the capability of configuring
the lower address bits A0, A1, and A2. The four upper address bits of the device are fixed at ‘1010’
(
see ST 24W32C data sheet).
The remaining three lower address bits of the seven bit I²C device
address are configurable using jumpers J13, J15 and J16. J16 sets address bit A0, J13 address bit
A1, and J15 address bit A2.
below shows the resulting seven bit I²C device address for the eight possible jumper
configurations.
Table 12: U12 EEPROM I²C address via J13, J15, and J16
1
U12
I²C
D
EVICE
A
DDRESS
J15
J13
J16
1010 010
2 + 3
2 + 3
2 + 3
1010 011
2 + 3
2 + 3
1 + 2
1010 000
2 + 3
1 + 2
2 + 3
1010 001
2 + 3
1 + 2
1 + 2
1010 110
1 + 2
2 + 3
2 + 3
1010 111
1 + 2
2 + 3
1 + 2
1010 100
1 + 2
1 + 2
2 + 3
1010 101
1 + 2
1 + 2
1 + 2
7.5.2
EEPROM Write Protection Control (J1)
Jumper J1 controls write access to the EEPROM (U12) device. Closing this jumper allows write
access to the device, while opening this jumper enables write protection.
The following configurations are possible:
Table 13: EEPROM write protection states via J1
1
EEPROM
W
RITE
P
ROTECTION
S
TATE
J1
Write access allowed
closed
Write protected
open
1
Defaults are in
bold blue
text
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